DMA (direct memory access) coalescing
First Claim
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1. A method comprising, at a device having at least one Direct Memory Access (DMA) engine:
- determining a repeated, periodic DMA coalescing interval based, at least in part, on a time period of a power sleep state of a host platform that is calculated to permit at least a sufficient amount of power consumption savings to result;
buffering data received at the device in a FIFO (First-In-First-Out) queue during the repeated, periodic DMA coalescing interval; and
DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.
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Abstract
In general, in one aspect, a method includes determining a repeated, periodic DMA (Direct Memory Access) coalescing interval based, at least in part, on a power sleep state of a host platform. The method also includes buffering data received at the device in a FIFO (First-In-First-Out) queue during the interval and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval.
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Citations
17 Claims
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1. A method comprising, at a device having at least one Direct Memory Access (DMA) engine:
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determining a repeated, periodic DMA coalescing interval based, at least in part, on a time period of a power sleep state of a host platform that is calculated to permit at least a sufficient amount of power consumption savings to result; buffering data received at the device in a FIFO (First-In-First-Out) queue during the repeated, periodic DMA coalescing interval; and DMA-ing the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A network interface controller comprising:
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at least one PHY; at least one MAC (media access controller) communicatively coupled to the at least one PHY; at least at least one Direct Memory Access (DMA) engine to transfer packets received via the at least on PHY and at least one MAC to a host memory; logic to; determine a repeated, periodic DMA coalescing interval based, at least in part, on a time period of a power sleep state of a host platform that is calculated to permit at least a sufficient amount of power consumption savings to result; buffer data received at the device in a FIFO (First-In-First-Out) queue during the repeated, periodic DMA coalescing interval; and DMA the data enqueued in the FIFO to a memory external to the device after expiration of the repeated, periodic DMA coalescing interval. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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Specification