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Method for reducing latency in a solid-state memory system while maintaining data integrity

  • US 8,661,218 B1
  • Filed: 09/22/2011
  • Issued: 02/25/2014
  • Est. Priority Date: 10/18/2007
  • Status: Active Grant
First Claim
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1. A method of reducing latency in read operations from an array of N solid-state storage channels, where N equals n data storage channels plus p parity storage channels, where n is greater than one, and the p parity storage channels provide a fault tolerance for a loss of valid data from at least two of said N solid-state storage channels, the method comprising the steps of:

  • a. sending read commands to said array of N solid-state storage channels, each read command being sent to all of the N solid-state storage channels simultaneously;

    b. performing a read operation for each read command from all of said array of N solid-state storage channels to provide requested data;

    c. identifying said read operation has completed on N−

    1 of said solid-state storage channels;

    d. determining integrity of data read form said N−

    1 solid-state storage channels;

    e. if said data read from said N−

    1 solid-state storage channels is valid, reconstructing data of a solid-state storage channel not having completed said read operation, and transferring said requested data to a processor requesting said data, and if said data read from said N−

    1 solid-state storage channels is invalid, waiting for all of the solid-state storage channels to then complete said read operation and determining integrity of data read from all said N solid-state storage channels;

    f. reconstructing data of any one solid-state storage channel found to be invalid from said determination of integrity of said data read from all said N solid-state channels; and

    g. repeating said steps (a)-(f) responsive to data from more than one solid-state channel being found to be invalid to correct for soft data errors.

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