Method for reducing latency in a solid-state memory system while maintaining data integrity

• US 8,661,218 B1
• Filed: 09/22/2011
• Issued: 02/25/2014
• Est. Priority Date: 10/18/2007
• Status: Active Grant

• Current Assignee: DataDirect Networks Incorporated
• Original Assignee: DataDirect Networks Incorporated
• Inventors: Piszczek, Michael, Manning, J. Gordon, Fernandes, Cedric
• Primary Examiner(s): Parikh, Kalpit
• Application Number:
  US13/240,507
• Time in Patent Office: 887 Days
• Field of Search: 711/103, 711/114, 711/167, 714/6.24, 714/748
• US Class Current: 711/167
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/1088 Reconstruction on already foreseen single or plurality of spare disks
• CPC Class Codes: G06F 2211/1057 Parity-multiple bits-RAID6, i.e. RAID 6 implementations

Abstract

A latency reduction method for read operations of an array of N solid-state storage devices having n solid-state storage devices for data storage and p solid-state storage devices for storing parity data is provided. Utilizing the parity generation engine fault tolerance for a loss of valid data from at least two of the N solid-state storage devices, the integrity of the data is determined when N−1 of the solid-state storage devices have completed executing a read command. If the data is determined to be valid, the missing data of the N^th solid-state storage device is reconstructed and the data transmitted to the requesting processor. By that arrangement the time necessary for the N^th solid-state storage device to complete execution of the read command is saved, thereby improving the performance of the solid-state memory system.

Claims

1. A method of reducing latency in read operations from an array of N solid-state storage channels, where N equals n data storage channels plus p parity storage channels, where n is greater than one, and the p parity storage channels provide a fault tolerance for a loss of valid data from at least two of said N solid-state storage channels, the method comprising the steps of:

a. sending read commands to said array of N solid-state storage channels, each read command being sent to all of the N solid-state storage channels simultaneously;

b. performing a read operation for each read command from all of said array of N solid-state storage channels to provide requested data;

c. identifying said read operation has completed on N−

1 of said solid-state storage channels;

d. determining integrity of data read form said N−

1 solid-state storage channels;

e. if said data read from said N−

1 solid-state storage channels is valid, reconstructing data of a solid-state storage channel not having completed said read operation, and transferring said requested data to a processor requesting said data, and if said data read from said N−

1 solid-state storage channels is invalid, waiting for all of the solid-state storage channels to then complete said read operation and determining integrity of data read from all said N solid-state storage channels;

f. reconstructing data of any one solid-state storage channel found to be invalid from said determination of integrity of said data read from all said N solid-state channels; and

g. repeating said steps (a)-(f) responsive to data from more than one solid-state channel being found to be invalid to correct for soft data errors.

2. The method as recited in claim 1, wherein the step of performing a read operation for each read command includes the step of respectively transferring data read from said plurality of solid-state storage channels to corresponding solid state storage channel memories.

3. The method as recited in claim 2, wherein the step of determining the integrity of data read from said N−

1 solid-state storage channels includes the step of using a dual parity generation engine to perform a parity check of said data read from said N−

1 solid-state storage channels.

4. The method as recited in claim 3, wherein the step of using a dual parity generation engine to perform a parity check includes the step of using said dual parity generation engine to transfer said data read from N−

1 of said solid-state storage channel memories to a buffer memory while performing said parity check.

5. The method as recited in claim 4, wherein the step of determining the integrity of data includes the step of removing said data read from said N−

1 solid-state storage channels from said buffer memory responsive to a determination that said data read from said N−

1 solid-state storage channels is invalid.

6. The method as recited in claim 1, wherein the step of determining integrity of data includes the step of using said data read from said N−

1 solid-state storage channels to regenerate said data from the solid-state storage channel not having completed said read operation responsive to determining said data read from said N−

1 solid-state storage devices is valid, and the step of reconstructing data of a solid-state storage channel not having completed said read operation is followed by the step of determining integrity of said reconstructed data.

7. The method as recited in claim 1, wherein the step of determining the integrity of data includes the step of using a dual parity generation engine to perform a parity check of said data read from said N−

1 solid-state storage channels.

8. A method of reducing latency in read operations from a plurality of solid-state storage devices arranged in N solid-state storage channels, where N is a number greater than 4, the method comprising the steps of:

a. providing a central control system for queuing commands for said N solid-state storage channels;

b. providing each solid-state storage channel with a buffer storage and a control system for controlling operation of a corresponding solid-state storage device, said control system being operable to receive a multiplicity of queued commands from said central control system and reorder an execution of said commands to minimize a latency of said corresponding solid-state storage device;

c. providing a parity engine coupled to said N solid-state storage channels, said parity engine utilizing data from at least two of said N solid-state storage channels to provide a fault tolerance for a loss of valid data from at least any two of said N solid-state storage channels;

d. sending read commands to said N solid-state channels, each read command being sent to all of the N solid-state channels simultaneously;

e. performing a read operation of each read command from all of said solid-state storage channels to provide requested data;

f. identifying said read operation has completed on N−

1 of said solid-state storage channels;

g. determining integrity of data read from said N−

1 solid-state storage channels;

h. if said data read from said N−

1 solid state storage channels is valid, reconstructing data of a solid-state storage channel not having completed said read operation and transferring said requested data to a processor requesting said requested data, and if said data read from said N−

1 solid-state storage channels is invalid, waiting for all solid-state storage channels to complete said read operation and determining integrity of data read from all said N solid-state storage channels;

i. reconstructing data of any one solid-state storage channel found to be invalid from said determination of integrity of said data read from all said N solid-state storage channels; and

j. repeating said steps (d)-(i) responsive to data from more than one solid-state storage channel being found to be invalid to correct for soft data errors.

9. The method as recited in claim 8, wherein the step of performing a read operation of each read command includes the step of respectively transferring data read from said corresponding solid-state storage device of each solid-state storage channel to the buffer storage of the solid-state storage channel.

10. The method as recited in claim 9, wherein the step of determining integrity of data includes the step of using said parity engine to transfer said data contained in said buffer storage of said N−

1 solid-state storage channels to a stage buffer memory while performing a parity check of said data transferred from said buffer storage of said N−

1 solid-state storage channels.

11. The method as recited in claim 10, wherein the step of determining the integrity of data includes the step of removing said data contained in said stage buffer memory therefrom responsive to a determination that said data is invalid.

12. The method as recited in claim 8, wherein the step of determining integrity of data includes the step of using said data read from said N−

1 solid-state storage channels to regenerate said data from the solid-state storage channel not having completed said read operation responsive to determining said data read from said N−

1 solid-state storage channels is valid, and the step of reconstructing data of a solid-state storage channel not having completed said read operation is followed by the step of determining integrity of the reconstructed data.

13. The method as recited in claim 8, wherein the step of providing a parity engine includes the step of providing a dual parity generation engine to perform a parity check of said data read from said N−

1 solid-state storage channels.

14. A method of reducing latency in read operations from an array of solid-state storage devices arranged in N solid-state storage channels, where N is a number greater than 3, the method comprising the steps of:

a. providing at least two of said N solid-state storage channels for storage of parity data;

b. sending read commands to said N solid-state storage channels, each read command being sent to all of the N solid-state storage channels simultaneously;

c. performing a read operation for each read command from all of said N solid-state storage channels to provide requested data;

d. identifying said read operation has completed on N−

1 of said solid-state storage channels;

e. determining integrity of data read from said N−

1 solid-state storage channels;

f. if said data read from said N−

1 solid-state storage channels is valid, reconstructing data of a solid-state storage channel not having completed said read operation and transferring said requested data to a processor requesting said requested data, and if said data read from said N−

1 solid-state storage channels is invalid, waiting for all solid-state storage channels to complete said read operation, and determining if said data read from all said N solid-state channels is valid;

g. reconstructing data of any one solid-state storage channel found to be invalid from said determination of integrity of said data read from all said N solid-state storage channels; and

h. repeating said steps (b)-(g) responsive to data from more than one solid-state storage channel being found to be invalid to correct for soft data errors.

15. The method as recited in claim 14, wherein the step of performing a read operation for each read command includes the step of respectively transferring data read from said N solid-state storage channels to corresponding solid-state storage channel memories.

16. The method as recited in claim 15, wherein the step of determining the integrity of data includes the step of using a dual parity generation engine to perform a parity check of said data read from said N−

1 solid-state storage channels.

17. The method as recited in claim 16, wherein the step of using a dual parity generation engine to perform a parity check includes the steps of using said dual parity generation engine to transfer said data read from said N−

1 solid-state storage channels to a stage buffer memory, and performing said parity check.

18. The method as recited in claim 17, wherein the step of determining the integrity of data includes the step of removing said data contained in said stage buffer memory therefrom responsive to a determination that said data read from said N−

1 solid-state storage channels is invalid.

19. The method as recited in claim 14, wherein the step of determining integrity of data includes the step of using said data read from said N−

1 solid-state storage channels to regenerate said data from the solid-state storage channel not having completed said read operation responsive to determining said data read from said N−

1 solid-state storage channels is valid, and the step of reconstructing data of a solid-state storage channel not having completed said read operation is followed by the step of determining integrity of the reconstructed data.

20. The method as recited in claim 14, wherein the step of determining the integrity of data includes the step of using a dual parity generation engine to perform a parity check of said data read from said N−

1 solid-state storage channels.