Wirelessly configurable memory device addressing

• US 8,661,224 B2
• Filed: 07/05/2012
• Issued: 02/25/2014
• Est. Priority Date: 01/31/2007
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Rofougaran, Ahmadreza, Markison, Timothy W.
• Primary Examiner(s): MACKALL, LARRY T
• Application Number:
  US13/542,284
• Publication Number:
  US 20120284481A1
• Time in Patent Office: 600 Days
• Field of Search: 711/170, 711/E12.084
• US Class Current: 711/170
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory device includes a plurality of memory modules and a memory management module. A memory module of the plurality of memory modules includes a plurality of memory cells and a memory millimeter wave (MMW) transceiver. The memory management module determines a main memory configuration for at least some of the plurality of memory modules. The memory management module also determines physical addresses for the main memory configuration and determines a MMW communication resource table that includes an allocation mapping of one or more MMW communication resources to one or more of the at least some of the plurality of memory modules.

Claims

1. A memory device comprises:

a plurality of memory modules, wherein a memory module of the plurality of memory modules includes a plurality of memory cells and a memory millimeter wave (MMW) transceiver; and

a memory management module operable to;

determine a memory configuration, wherein the memory configuration includes at least a portion of the plurality of memory modules;

store logical addresses and corresponding memory module identification codes for the portion of the plurality of memory modules in the memory configuration in a memory module table;

receive a memory access request that includes a logical address;

determine at least one corresponding memory module identification code for at least one of the memory modules in the memory configuration based on the logical address in the memory access request and the memory module table;

generate a memory module address message based on the memory access request and the at least one memory module identification code; and

access a MMW communication resource table to determine at least one MMW communication resource to address the at least one of the memory modules in the memory configuration.

2. The memory device of claim 1, wherein the memory management module is further operable to:

allocate one or more MMW communication resources for addressing the portion of the plurality of memory modules in the memory configuration; and

store a mapping of the allocated one or more MMW communication resources in the MMW communication resource table.

3. The memory device of claim 2, wherein the memory management module is further operable to:

retrieve a physical address corresponding to the logical address in the memory module table; and

determine the at least one corresponding memory module identification code for the at least one of the memory modules in the memory configuration that includes the physical address.

4. The memory device of claim 3, wherein the memory management module comprises:

a memory MMW transceiver operable to;

convert the memory module address message into a MMW signal in accordance with the at least one MMW communication resource; and

transmit the MMW signal to the at least one memory module via the at least one MMW communication resource.

5. The memory device of claim 4, wherein the memory MMW transceiver is further operable to:

receive an inbound MMW memory access signal;

convert the inbound MMW memory access signal into the memory access request; and

convey the memory access request to the memory management unit.

6. The memory device of claim 1, wherein the memory management module is operable to determine the memory configuration by at least one of:

accessing a pre-programmed default configuration;

accessing a look up table to determine the memory configuration from one of a plurality of configurations; and

determining memory addressability.

7. The memory device of claim 1, wherein the memory management module is operable to determine the memory configuration by:

at start-up of a device including the memory device;

determine start-up applications requiring access to a memory;

allocate the portion of the plurality of memory modules for the start-up applications; and

configure the portion of the plurality of memory modules in accordance with memory requirements of the start-up applications.

8. The memory device of claim 1, wherein the memory management module is operable to determine the memory configuration by:

during on-going operation of a device including the memory device;

determine active applications requiring access to the memory;

allocate the portion of the plurality of memory modules for the start-up applications; and

configure the portion of the plurality of memory modules in accordance with memory requirements of the active applications.

9. The memory device of claim 1, wherein the memory management module is operable to determine the memory configuration by:

allocating a first portion of the plurality of memory modules for user applications;

allocating a second portion of the plurality of memory modules for operating system applications; and

allocating a third portion of the plurality of memory modules for direct memory access.

10. The memory device of claim 1, wherein the memory management module is operable to determine the memory configuration by:

determining memory line size; and

determining the main memory configuration in accordance with the memory line size.

11. The memory device of claim 1, wherein the memory management module is operable to store logical addresses and the corresponding memory module identification codes for the portion of the plurality of memory modules in the memory configuration in the memory module table by:

storing a mapping of physical addresses and the corresponding memory module identification codes for the portion of the plurality of memory modules in the memory configuration in the memory module table; and

storing a mapping of the logical addresses to the physical addresses in the memory module table.

12. A device comprises:

a memory that includes a plurality of memory modules, wherein a memory module of the plurality of memory modules includes a plurality of memory cells and a memory MMW transceiver;

a memory management unit operable to;

receive a memory access request;

determine a memory module identification for one or more of the plurality of memory modules based on the memory access request; and

generate a memory module message that includes the memory module identification for the one or more of the plurality of memory modules and at least a portion of the memory access request;

a memory management MMW transceiver operable to;

convert the memory module message into a MMW memory access signal; and

transmit the MMW memory access signal to the one or more of the plurality of memory modules.

13. The device of claim 12, wherein the memory management unit is further operable to store logical addresses and corresponding memory module identifications for one or more of the plurality of memory modules in a memory module table.

14. The device of claim 13, wherein the memory management unit is further operable to:

interpret the memory access request to determine a logical address from the memory access request;

determine whether a current entry in the memory module table exists for the logical address; and

when a current entry exists, determine the memory module identification corresponding to the logical address.

15. The device of claim 14, wherein the memory management unit is operable to determine the memory module identification corresponding to the logical address by:

retrieving a physical addresses corresponding to the logical address in the memory module table; and

determining the memory module identification for the memory module that includes the physical address.

16. The device of claim 12, further comprising:

a processing module that includes;

a processing core operable to produce the memory access request;

processing core cache coupled to the processing core; and

a processing module millimeter wave (MMW) transceiver coupled to the processing core cache.

17. The device of claim 16, wherein the one or more of the plurality of memory modules is operable to:

receive the MMW memory access signal transmitted by the memory management MMW transceiver;

determine the at least the portion of the memory access request in the MMW memory access signal;

generate a memory access response;

convert the memory access response into a MMW memory response signal; and

transmit the MMW memory response signal to the processing core.

18. A device comprises:

a memory that includes a plurality of memory modules, wherein a memory module of the plurality of memory modules includes a plurality of memory cells and a memory MMW transceiver; and

a memory management unit operable to;

receive a memory access request;

determine an identification of one or more of the plurality of memory modules based on the memory access request;

generate a memory module message that includes the identification for the one or more of the plurality of memory modules and at least a portion of the memory access request;

allocate one or more MMW communication resources to use for addressing the plurality of memory modules in the memory;

store a mapping of the allocated one or more MMW communication resources in a MMW communication resource table; and

access the MMW communication resource table to determine a first MMW communication resource from the one or more MMW communication resources to transmit the memory module message to the one or more of the plurality of memory modules.

19. The memory device of claim 18, wherein the memory management unit is further operable to:

allocate one or more other MMW communication resources for transmissions by the plurality of memory modules in the memory to a processing module;

store a mapping of the allocated one or more other MMW communication resources in a MMW communication resource table;

access the MMW communication resource table to determine a second MMW communication resource for transmission by the one or more of the plurality of memory modules and the processing module; and

generate the memory module message to include the second MMW communication resource.

20. The memory device of claim 19, wherein the memory management unit is further operable to:

determine a memory configuration of the memory, wherein the memory configuration includes at least a portion of the plurality of memory modules in the memory; and

store logical addresses and corresponding identifications for the portion of the plurality of memory modules in the memory configuration in a memory module table.