Method and apparatus for performing delay annotation

• US 8,661,385 B1
• Filed: 09/07/2007
• Issued: 02/25/2014
• Est. Priority Date: 09/07/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Wysocki, Chris, Vanderhoek, Tim, Ludwin, Adrian, Carvalho, Lyndon Francis
• Primary Examiner(s): TAT, BINH C
• Application Number:
  US11/899,837
• Time in Patent Office: 2,363 Days
• Field of Search: 716 4- 6, 716106-109
• US Class Current: 716/113
• CPC Class Codes: G06F 2119/10 Noise analysis or noise optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A method for designing a system on a target device includes performing delay annotation where a first delay associated with a first aspect of the system is determined by a first software thread and a second delay associated with a second aspect of the system is determined by a second software thread and the first and second software threads operate in parallel. Ensuring independence between each aspect of the system will facilitate efficient parallelism (i.e. minimal synchronization) while still maintaining serial equivalency.

Claims

1. A method for designing a system on a target device, comprising:

determining a first delay associated with a first aspect of the system, wherein determining the first delay is performed by a first software thread; and

determining a second delay associated with a second aspect of the system, wherein determining the second delay is performed by a second software thread, wherein the first and second software threads are executed in parallel, and wherein at least one of the determinings is performed by a processor.

2. The method of claim 1, wherein the first aspect and the second aspect of the system relate to cell delay.

3. The method of claim 2, wherein the first and second delays are determined by referencing a table comprising delay information for a plurality of cell types.

4. The method of claim 1, wherein the first aspect and the second aspect of the system relate to routing delays of a first routing network and a second routing network.

5. The method of claim 4, further comprising:

creating descriptions of the first and the second routing networks of the system; and

placing each of the first and the second descriptions in a queue for determining an order of routing delay annotation on the first and the second routing networks.

6. The method of claim 4, wherein the first and the second routing networks each includes one or more routing elements between a first and second logic cell.

7. The method of claim 5, wherein creating description of the first and the second routing networks of the system comprises:

determining routing element connectivity of the first and the second routing networks; and

describing parasitic capacitive loading of the first and the second routing network.

8. The method of claim 7, wherein describing parasitic capacitive loading of the first and the second routing networks comprises:

storing and retrieving parasitic capacitive loading information of the first and the second routing networks in a separate configuration random access memory (CRAM) storage structure.

9. The method of claim 4, wherein the first software thread determines a value of the first delay as a delay of a routing element having properties of a routing element in the first routing network if the delay of the routing element has been computed.

10. The method of claim 9, further comprising:

determining whether properties of the routing element comprise an inferred grid point within an interpolation cache; and

computing the delay of the routing element by simulating the routing element in response to the properties of the routing element not comprising the inferred grid point.

11. The method of claim 9, further comprising:

determining whether properties of the routing element comprise an inferred grid point within an interpolation cache; and

computing the delay of the routing element by computing delays of neighboring grid points by simulation and interpolating a delay of a first routing element from the delays of the neighboring grid points in response to the properties of the routing element comprising the inferred grid point.

12. The method of claim 11, further comprising storing the delays of the neighboring grid points.

13. The method of claim 1, wherein the first aspect of the system relate to cell delay and the second aspect of the system relate to routing delay for a routing network.

14. The method of claim 1, further comprising:

synthesizing the system;

placing the system on the target device; and

routing the system on the target device.

15. The method of claim 1, wherein the first thread is executed on a first processor core and the second thread is executed on a second processor core.

16. A method for designing a system on a target device, comprising:

determining a first delay associated with a first routing network, wherein determining the first delay is performed by a first software thread; and

determining a second delay associated with a second routing network, wherein determining the second delay is performed by a second software thread, wherein the first and second software threads are executed in parallel, and wherein at least one of the determinings is performed by a processor.

17. The method of claim 16, wherein determining the first delay comprises:

converting a routing element in the first routing network to an inferred grid point where properties of the routing element are mappable onto a multi-dimensional grid at the inferred grid point.

18. The method of claim 17, wherein the properties include electrical properties and typological properties.

19. The method of claim 17, further comprising:

identifying neighboring grid points in a grid space of the inferred grid point; and

interpolating a delay value of the routing element from the neighboring grid points on the multi-dimensional grid.

20. The method of claim 17, wherein determining the second delay comprises:

converting a routing element on the second routing network to another inferred grid point where properties of the routing element on the second routing network are mappable onto a multi-dimensional grid.

21. The method of claim 17, wherein the first delay is a delay value of the inferred grid point if the delay value has been computed.

22. The method of claim 16, wherein the first thread is executed on a first processor core and the second thread is executed on a second processor core.

23. An article of manufacture comprising a machine accessible medium including sequences of instructions, the sequences of instructions including instructions which, when executed by the machine, causes the machine to perform a method comprising:

determining a first delay associated with a first aspect of a system, wherein determining the first delay is performed by a first software thread executed on a first processor core; and

determining a second delay associated with a second aspect of the system, wherein determining the second delay is performed by a second software thread executed on a second processor core, wherein the first and second software threads are executed in parallel.

24. A system designer, comprising:

a synthesis unit operable to generate a design for a system;

a mapping unit operable to identify available components on a target device for implementing the design;

a placement unit operable to identify a subset of the available components for assignment to the system;

a routing unit operable to identify routing resources on the target device for coupling the subset of the available components; and

a delay annotation unit operable to determine a first delay associated with a first aspect of the system and a second delay associated with a second aspect of the system, wherein the first and second delays are determined in parallel.

25. The apparatus of claim 24, wherein the first aspect and the second aspect of the system relate to cell delay.

26. The apparatus of claim 24, wherein the first aspect and the second aspect of the system relate to routing delays of a first routing network and a second routing network.

27. The apparatus of claim 24, wherein the delay annotation unit includes an interpolation cache operable to store delays of routing elements having specific configurations and operating conditions.

28. The apparatus of claim 24, wherein the delay annotation unit further includes a simulation unit operable to populate an interpolation cache with delays of routing elements.

29. The apparatus of claim 24, wherein the delay annotation unit further includes an interpolation unit operable to interpolate a delay for a routing element from delays stored in an interpolation cache.

30. The apparatus of claim 24, further comprising a design manager operable to perform timing analysis with delay information from the delay annotation unit.

31. The apparatus of claim 24, wherein the system designer is implemented by a computer system and the first delay is determined by a first thread executed on a first processor core and the second delay is determined by a second thread executed on a second processor core.