Methods and apparatus for managing and controlling power consumption and heat generation in computer systems

• US 8,661,446 B2
• Filed: 06/01/2011
• Issued: 02/25/2014
• Est. Priority Date: 04/05/2006
• Status: Active Grant

• Current Assignee: Data Device Corporation (Transdigm Group Incorporated)
• Original Assignee: Maxwell Technologies Incorporated (Tesla Inc.)
• Inventors: Conrad, Mark Steven, Hillman, Robert A.
• Primary Examiner(s): NGUYEN, VAN H
• Application Number:
  US13/150,948
• Publication Number:
  US 20110231684A1
• Time in Patent Office: 1,000 Days
• Field of Search: None
• US Class Current: 718/103
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for reducing power consumption and heat generation in a computer system employs a substitute idle task that puts the processor into a dormant mode, e.g., sleep, nap, or doze mode. The substitute idle task replaces a conventional operating system idle task. The substitute idle task may have a low priority, such as that of the conventional idle task, which it replaces. At each occurrence of a quantum interrupt, a task scheduler schedules applications for execution during the accompanying time slice. After the scheduled applications are done, the substitute idle task is executed. The dormant mode caused by the idle task reduces the system'"'"'s power consumption. The idle task may also have a high priority and be designed to run for a predetermined percentage of time. As the processor spends the predetermined percentage of time in the dormant mode, known power consumption reduction may be guaranteed in the system.

Claims

1. A method of operating a processor, the method comprising:

executing a task scheduler in a beginning of each of a periodic time slice interval of a plurality of time slice intervals to obtain a determination of scheduled applications and a schedule of application execution during said each said periodic time slice intervals, the plurality of time slice intervals constituting a continuous time period;

executing the scheduled applications in said each periodic time slice interval in accordance with the determination of scheduled applications and the schedule of application execution during said each periodic time slice interval; and

executing a substitute idle task upon completion of executing the scheduled applications in said each periodic time slice interval,

wherein the step of executing the substitute idle task comprises causing the processor to enter a dormant mode.

2. The method in accordance with claim 1, wherein the substitute idle task has an idle task priority that is lower than priority of each of the scheduled applications in said each periodic time slice interval.

3. The method in accordance with claim 1, wherein the substitute idle task has an idle task priority that is no higher than priority of all applications executed by the processor.

4. The method in accordance with claim 1, wherein the step of causing the processor to enter the dormant mode comprises causing the processor to enter a low latency period dormant mode.

5. The method in accordance with claim 1, wherein the step of causing the processor to enter the dormant mode comprises causing the processor to enter a low latency period dormant mode that requires fewer than fifty processor clock cycles to awaken the processor.

6. The method in accordance with claim 1, wherein the step of causing the processor to enter the dormant mode comprises causing the processor to enter a low latency period dormant mode that requires fewer than twenty processor clock cycles to awaken the processor.

7. The method in accordance with claim 1, wherein the step of causing the processor to enter the dormant mode comprises causing the processor to enter a low latency period dormant mode that requires no more than ten processor clock cycles to awaken the processor.

8. The method in accordance with claim 1, further comprising:

receiving a first non-operating system interrupt during the dormant mode caused by the substitute idle task; and

servicing the first non-operating system interrupt during the time slice in which the first non-operating system interrupt is received.

9. The method in accordance with claim 8, wherein the first non-operating system interrupt is generated by a stimulus event external to the computer system of the processor.

10. The method in accordance with claim 8, wherein the first non-operating system interrupt is generated by an event internal to the computer system of the processor.

11. The method in accordance with claim 8, further comprising executing the substitute idle task in response to completion of servicing the first non-operating system interrupt during the time slice in which the first non-operating system interrupt is received.

12. The method in accordance with claim 8, further comprising:

receiving a second non-operating system interrupt during the dormant mode caused by the substitute idle task executed in response to completion of servicing the first non-operating system interrupt; and

servicing the second non-operating system interrupt during the time slice in which the second non-operating system interrupt is received.

13. A method of operating a processor, the method comprising:

executing a task scheduler in a beginning of each periodic time slice interval of a plurality of time slice intervals to obtain a determination of scheduled applications and a schedule of application execution during said each periodic time slice interval,

the schedule of application execution during said each periodic time slice interval being arranged in accordance with priority levels of the scheduled applications for said each periodic time slice interval,

the plurality of time slice intervals constituting a continuous time period,

the scheduled applications comprising a substitute idle task configured to cause the processor to enter a first dormant mode,

the substitute idle task having an idle task priority level lower than each other scheduled application so that the substitute idle task is scheduled last during said each periodic time slice interval; and

executing the scheduled applications in said each periodic time slice interval in accordance with the determination of the scheduled applications and the schedule of application execution during said each periodic time slice interval.

14. The method in accordance with claim 13, wherein the first dormant mode is a low latency period dormant mode that requires fewer than fifty processor clock cycles to awaken the processor.

15. The method in accordance with claim 13, wherein the first dormant mode is a low latency period dormant mode that requires fewer than twenty processor clock cycles to awaken the processor.

16. The method in accordance with claim 13, wherein the first dormant mode is a low latency period dormant mode that requires no more than ten processor clock cycles to awaken the processor.

17. The method in accordance with claim 13, further comprising:

receiving a first non-operating system interrupt during the first dormant mode caused by the substitute idle task; and

servicing the first non-operating system interrupt during the time slice interval in which the first non-operating system interrupt is received.

18. The method in accordance with claim 17, further comprising executing the substitute idle task in response to completion of servicing the first non-operating system interrupt during the time slice interval in which the first non-operating system interrupt is received.

19. The method in accordance with claim 13, wherein the scheduled applications further comprise an OS level power limiting task configured to cause the processor to enter a second dormant mode, the OS level power limiting task having a priority level higher than each other scheduled application so that the OS level power limiting task is scheduled first during said each periodic time slice interval.

20. The method in accordance with claim 19, wherein the first dormant mode is the same as the second dormant mode.

21. The method in accordance with claim 19, wherein the first dormant mode is not the same as the second dormant mode.

22. A computer system comprising:

at least one processor; and

a memory storing program code, the memory being coupled to the at least one processor to allow the at least one processor to read the program code;

wherein the program code, when executed by the at least one processor, configures the at least one processor to cause the computer system to

execute a task scheduler in a beginning of each periodic time slice interval, the plurality of time slice intervals to obtain a determination of scheduled applications and a schedule of application execution for said each periodic time slice interval,

the schedule of application execution for said each periodic time slice interval being arranged in accordance with priority levels of the scheduled applications for said each periodic time slice interval, the plurality of time slice intervals constituting a continuous time period,

the scheduled applications of said each periodic time slice interval comprising a substitute idle task configured to cause the at least one processor to enter a dormant mode, the substitute idle task having an idle task priority level lower than each other scheduled application so that the substitute idle task is scheduled last during said each periodic time slice interval; and

execute the scheduled applications in said each periodic time slice interval in accordance with the determination of the scheduled applications and the schedule of application execution for said each periodic time slice interval.

23. The computer system in accordance with claim 22, wherein the dormant mode is a low latency period dormant mode.

24. The computer system in accordance with claim 22, wherein the dormant mode requires fewer than fifty processor clock cycles to awaken the at least one processor.

25. The computer system in accordance with claim 22, wherein the dormant mode requires fewer than twenty processor clock cycles to awaken the at least one processor.

26. The computer system in accordance with claim 22, wherein the dormant mode requires no more than ten processor clock cycles to awaken the at least one processor.

27. The computer system in accordance with claim 22, wherein the program code, when executed by the at least one processor, further configures the at least one processor to cause the computer system to receive a non-operating system interrupt during the dormant mode caused by the substitute idle task;

and service the non-operating system interrupt during the time slice interval in which the non-operating system interrupt is received.

28. The computer system in accordance with claim 27, wherein the program code, when executed by the at least one processor, further causes the processor to cause the computer system to execute the substitute idle task in response to completion of servicing the non-operating system interrupt during the time slice interval in which the non-operating system interrupt is received.

29. The computer system in accordance with claim 22, wherein the at least one processor comprises a plurality of processors and the computer system is a fault-tolerant computer system.