Securities, chip mounting product, and manufacturing method thereof

• US 8,662,402 B2
• Filed: 12/08/2011
• Issued: 03/04/2014
• Est. Priority Date: 12/26/2003
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Kato, Kiyoshi
• Primary Examiner(s): Frech, Karl D
• Application Number:
  US13/314,280
• Publication Number:
  US 20120074481A1
• Time in Patent Office: 817 Days
• Field of Search: 235/487, 235/494, 235/380, 235/375, 235/492
• US Class Current: 235/492
• CPC Class Codes: G06K 19/07749 the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
• CPC Class Codes: G06K 19/07758 arrangements for adhering the record carrier to further objects or living beings, functioning as an identification tag
• CPC Class Codes: G06K 19/07767 the first and second communication means being two different antennas types, e.g. dipole and coil type, or two antennas of the same kind but operating at different frequencies
• CPC Class Codes: G07D 7/01 Testing electronic circuits therein
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention provides an ID chip with reduced cost, increased impact resistance and attractive design, as well as products and the like mounting the ID chip and a manufacturing method thereof. In view of the foregoing, an integrated circuit having a semiconductor film with a thickness of 0.2 μm or less is mounted on securities including bills, belongings, containers of food and drink, and the like (hereinafter referred to as products and the like). The ID chip of the invention can be reduced in cost and increased in impact resistance as compared with a chip formed over a silicon wafer while maintaining an attractive design.

Claims

1. A semiconductor device comprising:

a circuit including;

a memory cell including a transistor;

a first wiring; and

a second wiring,

wherein one of a source and a drain of the transistor is connected to one of the first wiring and the second wiring through a conductive wiring discharged by an ink jet printing.

2. The semiconductor device according to claim 1, wherein the transistor is a thin film transistor.

3. The semiconductor device according to claim 1, wherein the memory cell is a non-volatile and non-rewritable memory cell.

4. A semiconductor device comprising a circuit including a first memory portion and a second memory portion,

wherein the first memory portion comprises:

a first memory cell including a first transistor;

a first wiring; and

a second wiring,

wherein the second memory portion comprises;

a second memory cell including a second transistor;

a third wiring; and

a fourth wiring,

wherein one of a source and a drain of the first transistor is directly connected to one of the first wiring and the second wiring formed by a photolithography, and

wherein one of a source and a drain of the second transistor is connected to one of the third wiring and the fourth wiring through a conductive wiring discharged by an ink jet printing.

5. The semiconductor device according to claim 4, wherein each of the first memory cell and the second memory cell is a non-volatile and non-rewritable memory cell.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor film over a substrate;

patterning the semiconductor film to form a first semiconductor layer and a second semiconductor layer;

forming a first bit line, a second bit line, a first wiring having a high potential, a second wiring having a low potential, and a third wiring by a photolithography method; and

forming a conductive wiring by an ink jet printing so that the third wiring is electrically connected to one of the first wiring and the second wiring through the conductive wiring,

wherein a first memory cell includes the first semiconductor layer,

wherein a second memory cell includes the second semiconductor layer,

wherein the first semiconductor layer is connected to the first bit line and one of the first wiring and the second wiring, and

wherein the second semiconductor layer is connected to the second bit line and the third wiring.

7. The method according to claim 6, wherein the high potential is VDD and the low potential is GND.

8. The method according to claim 6, wherein each of the first memory cell and the second memory cell is a non-volatile and non-rewritable memory cell.

9. The method according to claim 6,

wherein a mask is used in the step of forming the first bit line, the second bit line, the first wiring, the second wiring, and the third wiring by the photolithography method, and

wherein a mask is not used in the step of the conductive wiring by the ink jet printing.

10. The method according to claim 9,

wherein the mask used for the photolithography method is a photomask.

11. The method according to claim 6,

wherein a first semiconductor device is formed over a first substrate by the method according to claim 6,

wherein a second semiconductor device is formed over a second substrate by the method according to claim 6,

wherein, in a second memory cell of the first semiconductor device, a third wiring is connected to a first wiring through a conductive wiring, and

wherein, in a second memory cell of the second semiconductor device, a third wiring is connected to the second wiring through a conductive wiring.