Method for fabrication of configurable systems

• US 8,664,042 B2
• Filed: 05/14/2012
• Issued: 03/04/2014
• Est. Priority Date: 10/12/2009
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak C., Cronquist, Brian, Beinglass, Israel, de Jong, Jan Lodewijk
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US13/471,009
• Publication Number:
  US 20120223738A1
• Time in Patent Office: 659 Days
• Field of Search: 438/109, 438/110, 438/113, 438/128, 438/460, 438/462, 438/942, 257/E21.598, 257/E21.599, 257/E21.614
• US Class Current: 438/109
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01066 : Dysprosium [Dy]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13062 : Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H03K 19/177 : arranged in matrix form
• CPC Class Codes: H10B 10/00 : Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 : comprising a MOSFET load element

Abstract

A method to construct configurable systems, the method including: providing a first configurable system including a first die and a second die, where the connections between the first die and the second die include through-silicon-via (“TSV”), where the first die is diced from a first wafer using first dice lines; providing a second configurable system including a third die and a fourth die, where the connections between the third die and the fourth die include through-silicon-via (“TSV”), where the third die is diced from a third wafer using third dice lines; and processing the first wafer and the third wafer utilizing at least 20 masks that are the same; where the first dice lines are substantially different than the third dice lines, and where the second die includes a configurable I/O to connect the first configurable system to external devices.

Claims

1. A method to construct configurable systems, the method comprising:

providing a first configurable system comprising a first die and a second die,

wherein the connections between said first die and said second die comprise through-silicon-via (“

TSV”

),

wherein said first die is diced from a first wafer using first dice lines;

providing a second configurable system comprising a third die and a fourth die,

wherein the connections between said third die and said fourth die comprise through-silicon-via (“

TSV”

),

wherein said third die is diced from a third wafer using third dice lines; and

processing said first wafer and said third wafer utilizing at least 20 masks that are the same;

wherein said first dice lines are substantially different than said third dice lines, and

wherein said second die comprises a configurable I/O to connect said first configurable system to external devices.

2. The method to construct configurable systems according to claim 1, wherein said first die is a field programmable gate array (FPGA) die.

3. The method to construct configurable systems according to claim 1, wherein said fourth die comprises a configurable I/O die.

4. The method to construct configurable systems according to claim 1, wherein said first die comprises a configurable memory die.

5. The method to construct configurable systems according to claim 1, wherein said first die comprises a repeating array of functional units.

6. The method to construct configurable systems according to claim 1, wherein said first die comprises a repeating array of functional units, wherein each of said functional units comprises a micro controller unit (MCU).

7. The method to construct configurable systems according to claim 1, wherein said first die comprises unused dice lines.

8. The method to construct configurable systems according to claim 1, wherein said diced comprises an etch step to define dice lines as a post process step.

9. A method to construct configurable systems, the method comprising:

providing a first configurable system comprising a first die and a second die;

wherein the connections from said first die to said second die comprise through-silicon vias (TSV),

wherein said first die is diced from a first wafer using first dice lines,

wherein said first dice lines are selected from a plurality of predefined potential dice lines, and

wherein said first die comprises unused dice lines, and

wherein said second die comprises unused dice lines,

providing a second configurable system comprising a third die and a fourth die,

wherein the connections between said third die and said fourth die comprise through-silicon-vias (“

TSV”

),

wherein said third die is diced from a third wafer using third dice lines; and

processing said first wafer and said third wafer utilizing at least 20 masks that are the same;

wherein said first dice lines are substantially different than said third dice lines.

10. A method to construct configurable systems according to claim 9, wherein said second die comprises a configurable memory.

11. A method to construct configurable systems according to claim 9, wherein said first die is a field programmable gate array (FPGA) die.

12. A method to construct configurable systems according to claim 9, wherein said first die comprises a configurable I/O die.

13. A method to construct configurable systems, the method comprising:

providing a first configurable system comprising a first die and a second die, wherein the connections between said first die and said second die comprise through-silicon-via (“

TSV”

),

wherein said first die is diced from a first wafer using first dice lines;

providing a second configurable system comprising a third die and a fourth die,

wherein the connections between said third die and said fourth die comprise through-silicon-via (“

TSV”

),

wherein said third die is diced from a third wafer using third dice lines; and

processing said first wafer and said third wafer utilizing at least 20 masks that are the same;

wherein said first dice lines are substantially different than said third dice lines, and

wherein said second die comprises a configurable I/O to connect said first configurable system to external devices, and

wherein said fourth die comprises a SerDes circuit.

14. The method to construct configurable systems according to claim 13, wherein said first die is a field programmable gate array (FPGA) die.

15. The method to construct configurable systems according to claim 13, wherein said fourth die comprises a configurable I/O die.

16. The method to construct configurable systems according to claim 13, wherein said first die comprises a configurable memory die.

17. The method to construct configurable systems according to claim 13, wherein said first die comprises a repeating array of functional units.

18. The method to construct configurable systems according to claim 13, wherein said first die comprises a repeating array of functional units, and wherein each of said functional units comprises a micro controller unit (MCU).

19. The method to construct configurable systems according to claim 13, wherein said diced comprises an etch step to define dice lines as a post process step.

20. The method to construct configurable systems according to claim 13, wherein said first die comprises unused dice lines.