Vertical ESD protection device

• US 8,664,080 B2
• Filed: 05/22/2012
• Issued: 03/04/2014
• Est. Priority Date: 05/25/2011
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tani, Toshiyuki, Springer, Lily, Yamasaki, Hiroshi, Takahashi, Kentaro
• Primary Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US13/477,792
• Publication Number:
  US 20120299146A1
• Time in Patent Office: 651 Days
• Field of Search: 257/566, 257/591, 257/E27.053, 257/E29.02, 257/E21.546, 438/430
• US Class Current: 438/430
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12036 PN diode
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1461 MEMS

Abstract

A method for forming a vertical electrostatic discharge (ESD) protection device includes depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on the p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on the first n-type epitaxial layer. The first type epitaxial layer has a peak doping level which is at least double that of the second n-type epitaxial layer. A p+ layer is formed on the second n-type epitaxial layer. An etch step etches through the p+ layer and multi-layer n-type epitaxial layer to reach the substrate to form a trench. The trench is filled with a filler material to form a trench isolation region. A metal contact is formed on the p+ layer for providing contact to the p+ layer.

Claims

1. A method for forming a vertical electrostatic discharge (ESD) protection device, comprising:

depositing a multi-layer n-type epitaxial layer on a substrate having p-type surface including first epitaxial depositing to form a first n-type epitaxial layer on said p-type surface, and second epitaxial depositing to form a second n-type epitaxial layer formed on said first n-type epitaxial layer, wherein said first n-type epitaxial layer has a peak doping level which is at least double that of said second n-type epitaxial layer, said multi-layer n-type epitaxial layer providing an n-base for a PNP bipolar transistor of said vertical ESD protection device;

forming a p+ layer on said second n-type epitaxial layer;

etching through said p+ layer and said multi-layer n-type epitaxial layer to reach said substrate to form a trench;

filling said trench with a filler material to form a trench isolation region, and

forming a metal contact on said p+ layer for providing contact to said p+ layer.

2. The method of claim 1, wherein said peak doping level of said first n-type epitaxial layer is in a range from 1×

1017 cm-3 to 3×

1018 cm-3 and said peak doping level of said second n-type epitaxial layer is in a range from 1×

1016 cm-3 to 5×

1017 cm-3.

3. The method of claim 1, wherein said trench comprises a dielectric lined trench and said filler material comprises polysilicon.

4. The method of claim 1, wherein said multi-layer n-type epitaxial layer is from 1.5 μ

m to 5.0 μ

m thick.

5. The method of claim 1, wherein said substrate comprises bulk p-type silicon.

6. The method of claim 1, wherein said forming said p+ layer comprises blanket ion implantation and a peak doping level said p+ layer is from 5×

1018 to 2×

1019 cm-3.

7. The method of claim 1, further comprising third epitaxial depositing to form a third n-type epitaxial layer on said second n-type epitaxial layer, wherein said third n-type epitaxial layer has a peak doping level which is at least double that of said second n-type epitaxial layer.

8. A vertical ESD protection device, comprising:

a substrate having a p-type surface;

an multi-layer n-type epitaxial layer including a first n-type epitaxial layer on said p-type surface and a second n-type epitaxial layer on said first n-type epitaxial layer;

wherein said first n-type epitaxial layer has a peak doping level which is at least double that of said second n-type epitaxial layer, said multi-layer n-type epitaxial layer providing an n-base for a PNP bipolar transistor of said vertical ESD protection device;

forming a p+ layer on said second n-type epitaxial layer

a p+ layer on said second n-type epitaxial layer;

a trench isolation region through said p+ layer and said multi-layer n-type epitaxial layer to reach said substrate filled with a filler material, and

a metal contact contacting said p+ layer.

9. The vertical ESD protection device of claim 8, wherein said peak doping level of said first n-type epitaxial layer is in a range from 1×

1017 cm-3 to 5×

1018 cm-3 and said peak doping level of said second n-type epitaxial layer is in a range from 1×

1016 cm-3 to 5×

1017 cm-3.

10. The vertical ESD protection device of claim 8, wherein said trench comprises a dielectric lined trench and said filler material comprises polysilicon.

11. The vertical ESD protection device of claim 8, wherein said multi-layer n-type epitaxial layer is from 1.5 μ

m to 5.0 μ

m thick.

12. The vertical ESD protection device of claim 8, wherein said substrate comprises bulk p-type silicon.

13. The vertical ESD protection device of claim 8, wherein said p+ layer is a blanket layer having a peak doping level from 5×

1018 to 2×

1019 cm-3.

14. The vertical ESD protection device of claim 8, further comprising a third n-type epitaxial layer on said second n-type epitaxial layer, wherein said third n-type epitaxial layer has a peak doping level which is at least double that of said second n-type epitaxial layer.