Protruding post resistive memory devices
First Claim
1. A resistive memory device comprising:
- a substrate having a first region where isolation patterns and first active patterns are alternately arranged in a first direction, and a second region where linear second active patterns are extended in the first direction;
gate electrode structures arranged between the first region and the second region of the substrate, the gate electrode structures having a linear shape extended in the first direction;
first and second impurity regions in the first and second active patterns at both sides of each of the gate electrode structures;
a first metal silicide pattern having an isolated shape that is configured to contact an upper surface of the first impurity region;
a second metal silicide pattern configured to contact an upper surface of the second impurity region and extended in the first direction;
a bit line contact on the first metal silicide pattern;
a resistive structure connected to the bit line contact; and
a bit line connected to the resistive structure.
1 Assignment
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Accused Products
Abstract
A resistive memory device may include a substrate, gate electrode structures, a first impurity region, a second impurity region, a first metal silicide pattern and a second metal silicide pattern. The substrate may have a first region where isolation patterns and first active patterns may be alternately arranged in a first direction, and a second region where linear second active patterns may be extended in the first direction. The gate electrode structures may be arranged between the first region and the second region of the substrate. The first and second impurity regions may be formed in the first and second impurity regions. The first metal silicide pattern may have an isolated shape configured to make contact with an upper surface of the first impurity region. The second metal silicide pattern may make contact with an upper surface of the second impurity region.
23 Citations
15 Claims
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1. A resistive memory device comprising:
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a substrate having a first region where isolation patterns and first active patterns are alternately arranged in a first direction, and a second region where linear second active patterns are extended in the first direction; gate electrode structures arranged between the first region and the second region of the substrate, the gate electrode structures having a linear shape extended in the first direction; first and second impurity regions in the first and second active patterns at both sides of each of the gate electrode structures; a first metal silicide pattern having an isolated shape that is configured to contact an upper surface of the first impurity region; a second metal silicide pattern configured to contact an upper surface of the second impurity region and extended in the first direction; a bit line contact on the first metal silicide pattern; a resistive structure connected to the bit line contact; and a bit line connected to the resistive structure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A semiconductor device comprising:
a semiconductor substrate including an array of semiconductor posts protruding therefrom in a direction that is perpendicular to a face of the semiconductor substrate, a respective post including a pair of first opposing semiconductor sidewalls and a pair of second opposing semiconductor sidewalls, wherein the pair of first opposing semiconductor sidewalls is longer than the pair of second opposing semiconductor sidewalls, in the direction that is perpendicular to the face of the semiconductor substrate. - View Dependent Claims (11, 12, 13, 14, 15)
Specification