Protruding post resistive memory devices

• US 8,664,634 B2
• Filed: 08/30/2012
• Issued: 03/04/2014
• Est. Priority Date: 12/06/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Hyun-Ju, Lee, Jae-Kyu
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Schoenholtz, Joseph
• Application Number:
  US13/599,259
• Publication Number:
  US 20130140516A1
• Time in Patent Office: 551 Days
• Field of Search: None
• US Class Current: 257/5
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A resistive memory device may include a substrate, gate electrode structures, a first impurity region, a second impurity region, a first metal silicide pattern and a second metal silicide pattern. The substrate may have a first region where isolation patterns and first active patterns may be alternately arranged in a first direction, and a second region where linear second active patterns may be extended in the first direction. The gate electrode structures may be arranged between the first region and the second region of the substrate. The first and second impurity regions may be formed in the first and second impurity regions. The first metal silicide pattern may have an isolated shape configured to make contact with an upper surface of the first impurity region. The second metal silicide pattern may make contact with an upper surface of the second impurity region.

Claims

1. A resistive memory device comprising:

a substrate having a first region where isolation patterns and first active patterns are alternately arranged in a first direction, and a second region where linear second active patterns are extended in the first direction;

gate electrode structures arranged between the first region and the second region of the substrate, the gate electrode structures having a linear shape extended in the first direction;

first and second impurity regions in the first and second active patterns at both sides of each of the gate electrode structures;

a first metal silicide pattern having an isolated shape that is configured to contact an upper surface of the first impurity region;

a second metal silicide pattern configured to contact an upper surface of the second impurity region and extended in the first direction;

a bit line contact on the first metal silicide pattern;

a resistive structure connected to the bit line contact; and

a bit line connected to the resistive structure.

2. The resistive memory device of claim 1, wherein the substrate has recesses, and the gate electrode structures are formed in the recesses.

3. The resistive memory device of claim 1, wherein the gate electrode structures are three in number linearly extended in the first direction between the second active patterns.

4. The resistive memory device of claim 1, wherein gate electrode structures among the gate electrode structures adjacent to the second active patterns serve as a gate electrode of a cell selection transistor, and a central gate electrode structure among the gate electrode structures serves as a gate electrode of an isolated transistor.

5. The resistive memory device of claim 1, wherein the second metal silicide pattern corresponds to a source line connected to a source region of a transistor.

6. The resistive memory device of claim 1, further comprising a conductive pattern on the second metal silicide pattern.

7. The resistive memory device of claim 1, wherein the first metal silicide pattern has a thickness substantially the same as that of the second metal silicide pattern.

8. The resistive memory device of claim 1, wherein the second impurity region has a lower surface lower than that of the first impurity region.

9. The resistive memory device of claim 1, wherein the second metal silicide pattern has a thickness greater than that of the first metal silicide pattern.

10. A semiconductor device comprising:

a semiconductor substrate including an array of semiconductor posts protruding therefrom in a direction that is perpendicular to a face of the semiconductor substrate, a respective post including a pair of first opposing semiconductor sidewalls and a pair of second opposing semiconductor sidewalls, wherein the pair of first opposing semiconductor sidewalls is longer than the pair of second opposing semiconductor sidewalls, in the direction that is perpendicular to the face of the semiconductor substrate.

11. The semiconductor device of claim 10, further comprising an isolation pattern that extends between the first opposing semiconductor sidewalls of adjacent ones of the array of semiconductor posts.

12. The semiconductor device of claim 11, further comprising an electrode pattern that extends between the second opposing semiconductor sidewalls of adjacent ones of the array of semiconductor posts.

13. The semiconductor device of claim 12, further comprising an array of memory cells, a respective one of which is on, and electrically connected to, a respective one of the semiconductor posts.

14. The semiconductor device of claim 13, wherein the array of memory cells comprises an array of resistive memory cells.

15. The semiconductor device of claim 14, wherein the electrode pattern comprises an insulating layer on the second opposing semiconductor sidewalls of adjacent ones of the array of semiconductor posts and a gate electrode on the insulating layer.