Semiconductor device and method for manufacturing semiconductor device
First Claim
1. A processor comprising:
- a register array;
an arithmetic logic unit operationally connected to the register array; and
an instruction register operationally connected to the arithmetic logic unit,wherein at least one of the register array, the arithmetic logic unit and the instruction register comprises a first transistor and a second transistor over the first transistor,wherein a channel formation region of the first transistor comprises silicon,wherein a channel formation region of the second transistor comprises an oxide semiconductor, andwherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor.
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Accused Products
Abstract
Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.
120 Citations
18 Claims
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1. A processor comprising:
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a register array; an arithmetic logic unit operationally connected to the register array; and an instruction register operationally connected to the arithmetic logic unit, wherein at least one of the register array, the arithmetic logic unit and the instruction register comprises a first transistor and a second transistor over the first transistor, wherein a channel formation region of the first transistor comprises silicon, wherein a channel formation region of the second transistor comprises an oxide semiconductor, and wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A processor comprising:
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a register array; an arithmetic logic unit operationally connected to the register array; and an instruction register operationally connected to the arithmetic logic unit, wherein at least one of the register array, the arithmetic logic unit and the instruction register comprises a first transistor and a second transistor over the first transistor, wherein a channel formation region of the first transistor comprises silicon, wherein a channel formation region of the second transistor comprises an oxide semiconductor, wherein a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor, and wherein a gate electrode of the second transistor is formed over the channel formation region of the second transistor. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification