Semiconductor device

• US 8,664,658 B2
• Filed: 05/05/2011
• Issued: 03/04/2014
• Est. Priority Date: 05/14/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yoneda, Seiichi
• Primary Examiner(s): TSAI, HUI JEY
• Application Number:
  US13/101,266
• Publication Number:
  US 20110278564A1
• Time in Patent Office: 1,034 Days
• Field of Search: 257/371, 257/393, 257/402, 257 57- 59, 257 66- 72, 257368-369, 257/E29.273
• US Class Current: 257/57
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1229 with different crystal properties within a device or between different devices
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs

Abstract

An n-channel transistor or a p-channel transistor provided with a second gate electrode for controlling a threshold voltage in addition to a normal gate electrode is used for a complementary logic circuit. In addition, an insulated gate field-effect transistor with an extremely low off-state current is used as a switching element to control the potential of the second gate electrode. A channel formation region of the transistor which functions as a switching element includes a semiconductor material whose band gap is wider than that of a silicon semiconductor and whose intrinsic carrier density is lower than that of silicon.

Claims

1. A semiconductor device comprising:

a first transistor, the first transistor being an n-channel transistor, and a first gate of the first transistor being electrically connected to a first wiring to which a first signal is supplied;

a second transistor, the second transistor being a p-channel transistor, a first gate of the second transistor being electrically connected to a second wiring to which a second signal is supplied, and one of a source and a drain of the second transistor being electrically connected to one of a source and a drain of the first transistor;

an insulating film over the first transistor and the second transistor; and

a third transistor over the insulating film,

wherein one of the first transistor and the second transistor comprises a second gate,

wherein the second gate is electrically connected to one of a source and a drain of the third transistor, and

wherein a channel formation region of the third transistor comprises an oxide semiconductor layer.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

3. The semiconductor device according to claim 1, wherein a hydrogen concentration in the channel formation region of the third transistor is less than or equal to 5×

10¹⁹ atoms/cm³.

4. The semiconductor device according to claim 1, wherein a value obtained by dividing an off-state current by a channel width of the third transistor is lower than or equal to 100 zA/μ

m.

5. The semiconductor device according to claim 1,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring to which a first potential is supplied, and the other of the source and the drain of the first transistor is electrically connected to a fourth wiring to which a second potential is supplied, and

wherein the first potential is higher than the second potential.

12. The semiconductor device according to claim 1, wherein a logical value of the first signal is the same as a logical value of the second signal.

13. The semiconductor device according to claim 1, wherein a gate of the third transistor is electrically connected to a fifth wiring to which a third signal is supplied, and the other of the source and the drain of the third transistor is electrically connected to a sixth wiring to which a fourth signal is supplied.

6. A semiconductor device comprising:

a first transistor, the first transistor being an n-channel transistor, and a first gate of the first transistor being electrically connected to a first wiring to which a first signal is supplied;

a second transistor, the second transistor being a p-channel transistor, a first gate of the second transistor being electrically connected to a second wiring to which a second signal is supplied, and one of a source and a drain of the second transistor being electrically connected to one of a source and a drain of the first transistor;

an insulating film over the first transistor and the second transistor; and

a third transistor over the insulating film,

wherein one of the first transistor and the second transistor comprises a second gate,

wherein the second gate is electrically connected to one of a source and a drain of the third transistor,

wherein a channel formation region of the third transistor comprises an oxide semiconductor layer, and

wherein a channel formation region of each of the first transistor and the second transistor comprises silicon.

7. The semiconductor device according to claim 6, wherein the oxide semiconductor layer comprises an In—

Ga—

Zn—

O-based oxide semiconductor.

8. The semiconductor device according to claim 6, wherein a hydrogen concentration in the channel formation region of the third transistor is less than or equal to 5×

10¹⁹ atoms/cm³.

9. The semiconductor device according to claim 6, wherein a value obtained by dividing an off-state current by a channel width of the third transistor is lower than or equal to 100 zA/μ

m.

10. The semiconductor device according to claim 6,

wherein the other of the source and the drain of the second transistor is electrically connected to a third wiring to which a first potential is supplied, and the other of the source and the drain of the first transistor is electrically connected to a fourth wiring to which a second potential is supplied, and

wherein the first potential is higher than the second potential.

14. The semiconductor device according to claim 6, wherein a logical value of the first signal is the same as a logical value of the second signal.

15. The semiconductor device according to claim 6, wherein a gate of the third transistor is electrically connected to a fifth wiring to which a third signal is supplied, and the other of the source and the drain of the third transistor is electrically connected to a sixth wiring to which a fourth signal is supplied.

16. The semiconductor device according to claim 6, wherein a band gap of the oxide semiconductor layer is wider than that of the silicon, and

wherein an intrinsic carrier density of the oxide semiconductor layer is lower than that of the silicon.

11. A semiconductor device comprising:

a first transistor, the first transistor being an n-channel transistor, and a first gate of the first transistor being electrically connected to a first wiring to which a first signal is supplied;

a second transistor, the second transistor being a p-channel transistor, a first gate of the second transistor being electrically connected to a second wiring to which a second signal is supplied, and one of a source and a drain of the second transistor being electrically connected to one of a source and a drain of the first transistor;

an insulating film over the first transistor and the second transistor; and

a third transistor over the insulating film,

wherein a channel formation region of the third transistor comprises an oxide semiconductor layer, and

wherein a threshold voltage of one of the first transistor and the second transistor is controlled by setting a potential of a second gate included in the one of the first transistor and the second transistor or a substrate potential of the one of the first transistor and the second transistor.

17. The semiconductor device according to claim 11, wherein a logical value of the first signal is the same as a logical value of the second signal.

18. The semiconductor device according to claim 11, wherein a gate of the third transistor is electrically connected to a fifth wiring to which a third signal is supplied, and the other of the source and the drain of the third transistor is electrically connected to a sixth wiring to which a fourth signal is supplied.