Schottky diode employing recesses for elements of junction barrier array

• US 8,664,665 B2
• Filed: 09/11/2011
• Issued: 03/04/2014
• Est. Priority Date: 09/11/2011
• Status: Active Grant

• Current Assignee: Wolfspeed, Inc.
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Henning, Jason Patrick, Zhang, Qingchun, Ryu, Sei-Hyung, Agarwal, Anant, Palmour, John Williams, Allen, Scott
• Primary Examiner(s): CAMPBELL, SHAUN M
• Application Number:
  US13/229,752
• Publication Number:
  US 20130062620A1
• Time in Patent Office: 905 Days
• Field of Search: 257/77
• US Class Current: 257/77
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]

Abstract

The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the substrate. A junction barrier array is provided in the drift layer just below the Schottky layer. The elements of the junction barrier array are generally doped regions in the drift layer. To increase the depth of these doped regions, individual recesses may be formed in the surface of the drift layer where the elements of the junction barrier array are to be formed. Once the recesses are formed in the drift layer, areas about and at the bottom of the recesses are doped to form the respective elements of the junction barrier array.

Claims

1. A semiconductor device comprising:

a drift layer having a first surface with an active region and a plurality of junction barrier element recesses, the drift layer being doped with a doping material of a first conductivity type and associated with an edge termination region that is substantially laterally adjacent the active region and comprises an edge termination structure, wherein the edge termination region has an edge termination recess extending into the drift layer from the first surface and the edge termination structure comprises a plurality of guard rings formed in the edge termination recess;

a Schottky layer over the active region of the first surface to form a Schottky junction; and

a plurality of first doped regions that extend into the drift layer about corresponding ones of the plurality of junction barrier element recesses wherein the plurality of first doped regions are doped with a doping material of a second conductivity type, which is opposite the first conductivity type, and form an array of junction barrier elements in the drift layer below the Schottky junction.

2. The semiconductor device of claim 1 wherein each of the plurality of junction barrier element recesses has at least one side and a bottom and each of the plurality of first doped regions extends into the drift layer about the at least one side and the bottom of a corresponding one of the plurality of junction barrier element recesses.

3. The semiconductor device of claim 1 wherein junction barrier elements in the array of junction barrier elements are separated from one another within the drift layer.

4. The semiconductor device of claim 1 wherein a depth of at least one of the plurality of junction barrier element recesses is at least 0.1 microns.

5. The semiconductor device of claim 4 wherein a width of at least one of the plurality of junction barrier element recesses is at least 0.5 microns.

6. The semiconductor device of claim 1 wherein a width of at least one of the plurality of junction barrier element recesses is at least 0.5 microns.

7. The semiconductor device of claim 1 wherein the edge termination structure comprises a plurality of guard rings and the first surface of the drift layer comprises a plurality of guard ring recesses such that at least some of the plurality of guard rings are second doped regions that extend into the drift layer about corresponding ones of the plurality of guard ring recesses, and the second doped regions are doped with the doping material of the second conductivity type.

8. The semiconductor device of claim 7 wherein guard rings in the plurality of guard rings are separated from each other within the drift layer.

9. The semiconductor device of claim 1 wherein the plurality of guard rings are formed in a bottom surface of the edge termination recess.

10. The semiconductor device of claim 9 wherein the bottom surface of the edge termination recess comprises a plurality of guard ring recesses such that at least some of the plurality of guard rings are second doped regions that extend into the drift layer about corresponding ones of the plurality of guard ring recesses, and the second doped regions are doped with the doping material of the second conductivity type.

11. The semiconductor device of claim 10 wherein the edge termination recess and the plurality of guard rings extend substantially about the active region.

12. The semiconductor device of claim 9 wherein a recess well is formed in the drift layer below the bottom surface of the edge termination recess, and the recess well is doped with the doping material of the second conductivity type.

13. The semiconductor device of claim 9 wherein the active region is provided on a mesa in the drift layer and further comprising a mesa guard ring that extends substantially about the Schottky layer such that the mesa guard ring resides between the Schottky layer and the plurality of guard rings.

14. The semiconductor device of claim 13 wherein the first surface of the drift layer about the active region comprises a mesa guard ring recess such that the mesa guard ring is a second doped region that extends into the drift layer about the mesa guard ring recess, and the second doped region is doped with the doping material of the second conductivity type.

15. The semiconductor device of claim 1 wherein the Schottky layer is formed from a low barrier height capable metal.

16. The semiconductor device of claim 15 wherein the low barrier height capable metal of the Schottky layer comprises tantalum.

17. The semiconductor device of claim 15 wherein the low barrier height capable metal of the Schottky layer comprises at least one of a group consisting of titanium, chromium, and aluminum.

18. The semiconductor device of claim 15 wherein the low barrier height capable metal of the Schottky layer consists essentially of tantalum.

19. The semiconductor device of claim 1 wherein the Schottky junction has a barrier height of less than 0.9 electron volts.

20. The semiconductor device of claim 1 wherein the drift layer is formed over a thinned substrate that was thinned after the drift layer was formed and a cathode contact is formed over a bottom surface of the thinned substrate.

21. The semiconductor device of claim 1 wherein the drift layer is predominantly doped with the doping material of the first conductivity type in a graded fashion wherein the drift layer has a lower doping concentration near the first surface and an intentionally higher doping concentration near a second surface of the drift layer, the second surface being substantially opposite the first surface.

22. The semiconductor device of claim 1 wherein the drift layer comprises silicon carbide.

23. The semiconductor device of claim 1 wherein the drift layer and the Schottky layer are part of a Schottky diode.

24. The semiconductor device of claim 23 wherein when forward biased, the semiconductor device supports a DC current density of at least 440 amperes/cm.

25. The semiconductor device of claim 23 wherein when forward biased, the semiconductor device supports a DC current density of at least 500 amperes/cm.

26. The semiconductor device of claim 23 wherein a ratio of DC forward biased current density to reverse biased anode-cathode capacitance is at least 0.275 ampere/pico-Farad (A/pF), wherein a reverse biased anode-cathode voltage is determined when the Schottky diode is reverse biased to a point where the active region is essentially fully depleted.

27. The semiconductor device of claim 23 wherein a ratio of DC forward biased current density to reverse biased anode-cathode capacitance is at least 0.3 ampere/pico-Farad (A/pF), wherein a reverse biased anode-cathode voltage is determined when the Schottky diode is reverse biased to a point where the active region is essentially fully depleted.

28. The semiconductor device of claim 23 wherein a ratio of DC forward biased current density to reverse biased anode-cathode capacitance is at least 0.35 ampere/pico-Farad (A/pF), wherein a reverse biased anode-cathode voltage is determined when the Schottky diode is reverse biased to a point where the active region is essentially fully depleted.

29. The semiconductor device of claim 1 wherein the drift layer and the Schottky layer are part of a silicon carbide Schottky diode.