Interconnect structure containing non-damaged dielectric and a via gouging feature

• US 8,664,766 B2
• Filed: 04/27/2009
• Issued: 03/04/2014
• Est. Priority Date: 03/01/2006
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Chih-Chao, Spooner, Terry A., van der Straten, Oscar
• Primary Examiner(s): TORNOW, MARK W
• Application Number:
  US12/430,436
• Publication Number:
  US 20090206485A1
• Time in Patent Office: 1,772 Days
• Field of Search: 438/618, 438/645, 257/774, 257/E23.145
• US Class Current: 257/774
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/31105 Etching inorganic layers
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32131 by physical means only
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An interconnect structure including a gouging feature at the bottom of one of the via openings. The structure includes an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein. The conductively filled via is in contact with an exposed surface of the at least one conductive feature of a first interconnect level by an anchoring area. The conductively filled via is separated from the second dielectric material by a first diffusion barrier layer, and the conductively filled line is separated from the second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line.

Claims

1. A semiconductor structure comprising:

a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein;

a dielectric capping layer located on said first dielectric material and some, but not all, portions of the at least one conductive feature; and

an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein said conductively filled via is in contact with an exposed surface of the at least one conductive feature of said first interconnect level by an anchoring area, said conductively filled via is separated from said second dielectric material by a first diffusion barrier layer, and said conductively filled line is separated from said second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to said conductively filled line, and wherein said first diffusion barrier layer is present only on sidewalls of said second dielectric material and said dielectric capping layer within said at least one conductively filled via and only on some portions of an exposed upper surface of the at least one conductive feature, and wherein said second diffusion barrier layer is in direct contact with a sidewall of said second dielectric material in said at least one conductively filled line and is present in said at least one conductively filled line that is located above said conductively filled via, but absent from said at least one conductively filled via, and wherein an upper surface of said conductively filled line is coplanar with an upper surface of the second dielectric material.

2. The semiconductor structure of claim 1 wherein said first and second dielectric materials comprise the same or different dense low k dielectric having a dielectric constant of about 4.0 or less.

3. The semiconductor structure of claim 1 wherein said first and second dielectric materials comprise the same or different porous low k dielectric having a dielectric constant of about 2.8 or less.

4. The semiconductor structure of claim 1 wherein said second dielectric material comprises two different low k dielectric materials and said upper interconnect level has a hybrid structure with said conductively filled line embedded in a porous dielectric material, and said conductively filled via embedded in a dense dielectric material.

5. The semiconductor structure of claim 4 wherein said porous low k dielectric having a dielectric constant of about 2.8 or less, and said dense porous low k dielectric having a dielectric constant of about 4.0 or less.

6. The semiconductor structure of claim 1 wherein said dielectric capping layer comprises one of SiC, Si₄NH₃, SiO₂, a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N,H) or multilayers thereof.

7. The semiconductor structure of claim 1 wherein said at least one conductive feature embedded within said first dielectric material includes Cu or a Cu-containing alloy.

8. The semiconductor structure of claim 1 wherein said at least one conductively filled via and said at least one overlying conductively filled line comprise Cu or a Cu-containing alloy.

9. The semiconductor structure of claim 1 wherein said first diffusion barrier layer comprises a metal-containing material, an insulator or any combination thereof.

10. The semiconductor structure of claim 1 wherein said second continuous diffusion barrier layer comprises Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, W or WN.

11. The semiconductor structure of claim 1 wherein said second continuous diffusion barrier layer is absent from said conductively filled via, yet said conductively filled via is separated from said second dielectric material by said first diffusion barrier layer.

12. The semiconductor structure of claim 1 wherein said second continuous diffusion barrier is also present in said conductively filled via atop said first diffusion barrier layer.

13. The semiconductor structure of claim 1 wherein the total diffusion barrier thickness of said first diffusion barrier layer and said second continuous diffusion barrier layer within said conductively filled via is thicker than said second continuous diffusion barrier layer thickness within said conductively filled line.

14. The semiconductor structure of claim 1 further comprising an adhesion/plating seed layer located on said second continuous diffusion barrier layer in said at least one conductively filled line, and located on said first diffusion barrier layer in said at least one conductively filled via.

15. The semiconductor structure of claim 1 further comprising an adhesion/plating seed layer located on said second continuous diffusion barrier layer in said at least one conductively filled line, and located on said second diffusion barrier layer in said at least one conductively filled via.

16. The semiconductor structure of claim 14 wherein said adhesion/plating seed layer comprises one or combination of Ru, TaRu, Ir, Rh, Pt, Pd, Ta, Cu or alloys thereof.

17. A semiconductor structure comprising:

a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein;

a dielectric capping layer located on said first dielectric material and some, but not all, portions of the at least one conductive feature; and

an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein said conductively filled via is in contact with said at least one conductive feature in said at least one first interconnect level by an anchoring area, a metallic interfacial layer located directly on a surface of the at least on conductive feature within said anchoring area and is in contact with said conductively filled via, said conductively filled via is separated from said second dielectric material by a first diffusion barrier layer, and said conductively filled line is separated from said second dielectric material by a second continuous diffusion barrier layer thereby the second dielectric material includes no damaged regions in areas adjacent to said conductively filled line, and wherein said first diffusion barrier layer is present only on sidewalls of said second dielectric material and said dielectric capping layer within said at least one conductively filled via and only on some portions of an exposed upper surface of the at least one conductive feature, and wherein said second diffusion barrier layer is in direct contact with a sidewall of said second dielectric material in said at least one conductively filled line and is present in said at least one conductively filled line that is located above said conductively filled via, but absent from said at least one conductively filled via, and wherein an upper surface of said conductively filled line is coplanar with an upper surface of the second dielectric material.

18. The semiconductor structure of claim 17 wherein said metallic interfacial layer comprises one or combination of Co, TaN, Ta, Ti, TiN, Ru, Ir, Au, Rh, Pt, Pd, Ag or alloys thereof.