Conductive routings in integrated circuits using under bump metallization

• US 8,664,767 B2
• Filed: 04/24/2012
• Issued: 03/04/2014
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Jergovic, Ilija, Lacap, Efren M.
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US13/454,968
• Publication Number:
  US 20130037963A1
• Time in Patent Office: 679 Days
• Field of Search: 257/774, 257/773, 257/343, 257/401, 257/758, 257/E23.011, 438/629, 438/627
• US Class Current: 257/774
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region. At least one of the first conductive area or the first conductive region includes a first protrusion extending toward the second conductive area or second conductive region, respectively. Conductive vias connect the first conductive region to the second conductive area and connect the second conductive region to the first conductive area, and the vias include at least one via connected to the first protrusion.

Claims

1. An integrated circuit structure comprising:

a first conductive layer disposed on a substrate and providing first electrodes and second electrodes for a distributed transistor in the substrate;

a second conductive layer over the first conductive layer, the second conductive layer having a first conductive portion and a second conductive portion electrically isolated from the first conductive portion;

a third conductive layer over the second conductive layer, the third conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region, the first conductive region substantially located over the first conductive portion and the second conductive region substantially located over the second conductive portion;

a fourth conductive layer over the third conductive layer, the fourth conductive layer having a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region, at least one of the first conductive area or the first conductive region including a first protrusion extending toward the second conductive area or second conductive region, respectively;

first conductive vias connecting the first conductive region to the second conductive area and connecting the second conductive region to the first conductive area, the conductive vias including at least one via connected to the first protrusion;

second conductive vias connecting the first conductive region to the first conductive portion through apertures in the first conductive area and connecting the second conductive region to the second conductive portion through apertures in the second conductive region;

third conductive vias connecting the first conductive area to the first electrodes through apertures in the first conductive portion and connecting the second conductive area to the second electrodes through apertures in the second conductive portion; and

fourth conductive vias connecting the first conductive portion to the second electrodes and connecting the second conductive portion to the first electrodes.

2. The integrated circuit structure of claim 1, wherein the first conductive area includes the first protrusion extending toward the second conductive area.

3. The integrated circuit structure of claim 2, wherein the second conductive region includes a second protrusion extending toward the first conductive region, and the first conductive vias include at least one via connecting the first protrusion to the second protrusion.

4. The integrated circuit structure of claim 1, comprising an outermost passivation layer, wherein the fourth conductive layer comprises an under bump metallization layer disposed over the outermost passivation layer, and wherein the first conductive vias and the second conductive vias extend through the outermost passivation layer.

5. The integrated circuit structure of claim 4, further comprising a first flip-chip interconnect on the first conductive area of the under bump metallization layer and a second flip-chip interconnect on the second conductive area of the under bump metallization layer.

6. The integrated circuit structure of claim 1, wherein the first conductive region has a plurality of first protrusions extending toward the second conductive region, and the second conductive region has a plurality of second protrusions extending toward the first conductive region.

7. The integrated circuit structure of claim 6, wherein the first conductive area has a plurality of third protrusions extending toward the second conductive area, and the second conductive area has a plurality of fourth protrusions extending toward the first conductive area.

8. The integrated circuit structure of claim 7, wherein the first conductive vias include a first plurality of conductive vias connecting the plurality of first protrusions to the plurality of fourth protrusions and a second plurality of conductive vias connecting the plurality of second protrusions to the plurality of third protrusions.

9. The integrated circuit structure of claim 1, wherein the first electrodes and the second electrodes are disposed on the substrate in an alternating pattern.

10. The integrated circuit structure of claim 9, wherein the alternating pattern comprises alternating strips.

11. The integrated circuit structure of claim 10, wherein a density of the fourth conductive vias per unit length of the strips is greater than a density of the third conductive vias per unit length of the strips.

12. The integrated circuit structure of claim 1, wherein the first electrodes are source electrodes and the second electrodes are drain electrodes.