Operational time extension

• US 8,664,974 B2
• Filed: 01/21/2011
• Issued: 03/04/2014
• Est. Priority Date: 12/01/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Schmit, Herman, Redgrave, Jason, Caldwell, Andrew, Rohe, Andre, Teig, Steven
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US13/011,840
• Publication Number:
  US 20110181317A1
• Time in Patent Office: 1,138 Days
• Field of Search: 326 37- 41, 326/47, 326/101, 716/126, 716/138
• US Class Current: 326/38
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.

Claims

1. An integrated circuit (“

IC”

) comprising;

a plurality of configurable circuits that operate in a plurality of operational cycles; and

at least one signal path through a set of the configurable circuits, wherein a particular signal is supplied for more than one operational cycles to a particular configurable circuit so that the particular configurable circuit can complete an operation in more than one operational cycles in order to allow the particular signal to traverse the signal path within a time constraint.

2. The IC of claim 1, wherein the particular signal is supplied to the particular configurable circuit in both a first operational cycle and a second operational cycle.

3. The IC of claim 2 further comprising a state element on the signal path to provide the particular signal to the particular configurable circuit in the first and second operational cycles.

4. The IC of claim 3, wherein the state element is configured to pass the particular signal to the particular configurable circuit in the first operational cycle and hold the particular signal for the particular configurable circuit in the second operational cycle.

5. The IC of claim 4, wherein the state element receives a control signal, wherein the state element passes the particular signal when the control signal is at a first level and holds the particular signal when the control signal is at a second level.

6. The IC of claim 1, wherein the timing constraint is a requirement that all operations in the signal path be completed within a particular time duration.

7. The IC of claim 1 further comprising a configurable storage circuit configured to supply the particular signal for more than one operational cycles to the particular configurable circuit in order to satisfy the timing constraint.

8. The IC of claim 2, wherein the particular configurable circuit is a logic circuit that reconfigures between the first and second operational cycles.

9. The IC of claim 2, wherein the first and second operational cycles are sub-cycles of a design cycle of a user design implemented by the IC.

10. The IC of claim 3, wherein the state element is a latch.

11. A method of mapping an integrated circuit (“

IC”

) design to an IC comprising a plurality of reconfigurable circuits performing a plurality of configurable operations in a plurality of operational cycles, the method comprising;

identifying a signal path through a plurality of reconfigurable circuits that requires a signal propagation time longer than a desired time period;

identifying a particular configurable circuit in the identified signal path at which the desired time period expires before the particular configurable circuit completes propagating a particular signal; and

supplying the particular signal for more than one operational cycles to the particular configurable circuit so that the particular configurable circuit can complete operation in more than one operational cycles in order to allow the signal to travel through the signal path within the desired time period.

12. The method of claim 11, wherein the particular signal is supplied to the particular configurable circuit in both a first operational cycle and a second operational cycle.

13. The method of claim 12, wherein the particular configurable circuit is a logic circuit that reconfigures between the first and second operational cycles.

14. The method of claim 12, wherein the first and second operational cycles are sub-cycles of a design cycle of a user design implemented by the IC.

15. The method of claim 12, wherein the particular signal is provided by a state element on the signal path.

16. The method of claim 15, wherein the state element is configured to pass the particular signal to the particular configurable circuit in the first operational cycle and hold the particular signal for the particular configurable circuit in the second operational cycle.

17. An electronic device comprising:

a memory device for providing configuration data; and

an integrated circuit (“

IC”

), the IC comprising;

a) a plurality of configurable circuits that operate in a plurality of operational cycles; and

b) at least one signal path through a set of the configurable circuits, wherein a particular signal is supplied for more than one operational cycles to a particular configurable circuit so that the particular configurable circuit can complete an operation in more than one operational cycles in order to allow the particular signal to traverse the signal path within a time constraint.

18. The electronic device of claim 17, wherein the particular signal is supplied to the particular configurable circuit in both a first operational cycle and a second operational cycle.

19. The electronic device of claim 18, the IC further comprising a state element on the signal path to provide the particular signal to the particular configurable circuit in the first and second operational cycles.

20. The electronic device of claim 19, wherein the state element is configured to pass the particular signal to the particular configurable circuit in the first operational cycle and hold the particular signal for the particular configurable circuit in the second operational cycle.