Semiconductor device and electronic device including semiconductor device

• US 8,664,981 B2
• Filed: 10/26/2012
• Issued: 03/04/2014
• Est. Priority Date: 03/26/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kimura, Hajime, Umezaki, Atsushi
• Primary Examiner(s): Wells, Kenneth B.
• Application Number:
  US13/661,165
• Publication Number:
  US 20130043911A1
• Time in Patent Office: 494 Days
• Field of Search: 327/108, 326/87
• US Class Current: 327/108
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H03K 19/00369 Modifications for compensating variations of temperature, supply voltage or other physical parameters

Abstract

It is an object to suppress deterioration in characteristics of a transistor in a driver circuit. A driver circuit includes a first transistor, a second transistor including a gate and one of a source and a drain to which a second signal is inputted, a third transistor whose gate is electrically connected to one of a source and a drain of the first transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off, and a fourth transistor whose gate is electrically connected to the other of the source and the drain of the second transistor and which controls whether a voltage state of an output signal is set or not by being turned on/off.

Claims

1. A semiconductor device comprising:

a first wiring configured to be inputted a first input signal;

a second wiring configured to be inputted a second input signal;

a third wiring configured to be inputted a third input signal;

a fourth wiring;

a first transistor including a gate, a source and a drain;

a second transistor including a gate, a source and a drain;

a third transistor including a gate, a source and a drain;

a fourth transistor including a gate, a source and a drain;

a fifth transistor including a gate, a source and a drain; and

a sixth transistor including a gate, a source and a drain,

wherein one of the source and the drain of the fifth transistor is electrically connected to the first wiring;

wherein one of the source and the drain of the sixth transistor is electrically connected to the first wiring;

wherein the gate and one of the source and the drain of the first transistor are electrically connected to the other of the source and the drain of the fifth transistor,

wherein the gate and one of the source and the drain of the second transistor are electrically connected to the other of the source and the drain of the sixth transistor,

wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein one of the source and the drain of the third transistor are electrically connected to the second wiring,

wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor,

wherein one of the source and the drain of the fourth transistor is electrically connected to the third wiring,

wherein the fourth wiring is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor, and

wherein a voltage which is given to the fourth wiring is a voltage of an output signal.

2. A semiconductor device according to claim 1, wherein a channel width of the first transistor is equal to a channel width of the second transistor.

3. A semiconductor device according to claim 1, wherein a channel width of the third transistor is equal to a channel width of the fourth transistor.

4. A semiconductor device according to claim 1,

wherein a channel width of the first transistor is smaller than a channel width of the third transistor, and

wherein a channel width of the second transistor is smaller than a channel width of the fourth transistor.

5. An electronic device comprising a semiconductor device according to claim 1 and an operation switch controlling an operation of the semiconductor device.

6. A semiconductor device comprising:

a first wiring configured to be inputted a first input signal;

a second wiring configured to be inputted a second input signal;

a third wiring;

a first transistor including a gate, a source and a drain;

a second transistor including a gate, a source and a drain;

a third transistor including a gate, a source and a drain; and

a fourth transistor including a gate, a source and a drain,

wherein the gate and one of the source and the drain of the first transistor are electrically connected to the first wiring,

wherein the gate and one of the source and the drain of the second transistor are electrically connected to the second wiring,

wherein the gate and one of the source and the drain of the third transistor are electrically connected to the other of the source and the drain of the first transistor,

wherein the gate and one of the source and the drain of the fourth transistor are electrically connected to the other of the source and the drain of the second transistor,

wherein the third wiring is electrically connected to the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor, and

wherein a voltage which is given to the third wiring is a voltage of an output signal.

7. A semiconductor device according to claim 6, wherein a channel width of the first transistor is equal to a channel width of the second transistor.

8. A semiconductor device according to claim 6, wherein a channel width of the third transistor is equal to a channel width of the fourth transistor.

9. A semiconductor device according to claim 6,

wherein a channel width of the first transistor is smaller than a channel width of the third transistor, and

wherein a channel width of the second transistor is smaller than a channel width of the fourth transistor.

10. An electronic device comprising a semiconductor device according to claim 6 and an operation switch controlling an operation of the semiconductor device.

11. A semiconductor device comprising:

a first wiring configured to be inputted a first input signal;

a second wiring configured to be inputted a second input signal;

a third wiring;

a first transistor including a gate, a source and a drain;

a second transistor including a gate, a source and a drain;

a first diode including a positive electrode and a negative electrode; and

a second diode including a positive electrode and a negative electrode,

wherein the gate and one of the source and the drain of the first transistor are electrically connected to the first wiring,

wherein the gate and one of the source and the drain of the second transistor are electrically connected to the second wiring,

wherein the positive electrode of the first diode is electrically connected to the other of the source and the drain of the first transistor,

wherein the positive electrode of the second diode is electrically connected to the other of the source and the drain of the second transistor,

wherein the third wiring is electrically connected to the negative electrode of the first diode and the negative electrode of the second diode, and

wherein a voltage which is given to the third wiring is a voltage of an output signal.

12. A semiconductor device according to claim 11, wherein a channel width of the first transistor is equal to a channel width of the second transistor.

13. An electronic device comprising a semiconductor device according to claim 11 and an operation switch controlling an operation of the semiconductor device.

14. A semiconductor device comprising:

a shift register comprising a flip-flop circuit comprising;

a first transistor including a gate, a source and a drain;

a second transistor including a gate, a source and a drain;

a third transistor including a gate, a source and a drain;

a fourth transistor including a gate, a source and a drain;

a fifth transistor including a gate, a source and a drain;

a sixth transistor including a gate, a source and a drain; and

a seventh transistor including a gate, a source and a drain,

wherein one of the source and the drain of the first transistor is electrically connected to a first input terminal,

wherein one of the source and the drain of the second transistor is electrically connected to a second input terminal,

wherein the gate of the first transistor is electrically connected to the one of the source and the drain of the first transistor,

wherein the gate of the second transistor is electrically connected to the one of the source and the drain of the second transistor,

wherein the gate of the third transistor is electrically connected to the other of the source and the drain of the first transistor,

wherein the gate of the fourth transistor is electrically connected to the other of the source and the drain of the second transistor,

wherein one of the source and the drain of the third transistor is electrically connected to a first line,

wherein one of the source and the drain of the fourth transistor is electrically connected to the first line,

wherein the other of the source and the drain of the third transistor is electrically connected to an output terminal,

wherein the other of the source and the drain of the fourth transistor is electrically connected to the output terminal,

wherein the gate of the fifth transistor is electrically connected to a third input terminal,

wherein the gate of the sixth transistor is electrically connected to the third input terminal,

wherein the gate of the seventh transistor is electrically connected to the third input terminal,

wherein one of the source and the drain of the fifth transistor is electrically connected to a second line,

wherein one of the source and the drain of the sixth transistor is electrically connected to the second line,

wherein one of the source and the drain of the seventh transistor is electrically connected to the second line,

wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the third transistor,

wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the fourth transistor, and

wherein the other of the source and the drain of the seventh transistor is electrically connected to the output terminal.

15. A semiconductor device according to claim 14, wherein a channel width of the first transistor is equal to a channel width of the second transistor.

16. A semiconductor device according to claim 14, wherein a channel width of the third transistor is equal to a channel width of the fourth transistor.

17. A semiconductor device according to claim 14,

wherein a channel width of the first transistor is smaller than a channel width of the third transistor, and

wherein a channel width of the second transistor is smaller than a channel width of the fourth transistor.

18. An electronic device comprising a semiconductor device according to claim 14 and an operation switch controlling an operation of the semiconductor device.