Dynamic power clamp for RFID power control

• US 8,665,007 B2
• Filed: 06/06/2012
• Issued: 03/04/2014
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ochoa, Agustin, Tang, Howard
• Primary Examiner(s): Donovan, Lincoln
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US13/490,254
• Publication Number:
  US 20120312881A1
• Time in Patent Office: 636 Days
• Field of Search: None
• US Class Current: 327/541
• CPC Class Codes: G06K 19/0715 the arrangement including means to regulate power transfer to the integrated circuit
• CPC Class Codes: H01L 27/0285 bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits H01L27/0281 takes precedence

Abstract

A clamp circuit for an RFID tag includes a power supply node, a dynamic clamp coupled between the power supply node and ground, and an active clamp coupled between the power supply and ground, having a shunt combined effect for providing a clamped power supply node VDDR voltage. The dynamic clamp includes a capacitor divider circuit, a resistor coupled to the capacitor divider circuit, and an N-channel transistor coupled to the capacitor divider circuit. The active clamp includes a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and an output coupled to a P-channel transistor for the clamped VDDR voltage.

Claims

1. A clamp circuit for an RFID tag comprising:

a power supply node;

a dynamic clamp coupled between the power supply node and ground; and

an active clamp coupled between the power supply node and ground, wherein the combined action of the dynamic and active clamps moderate the behavior of the power supply node to fast rising RF inputs,

wherein the active clamp comprises a differential amplifier having a first input coupled to a resistor divider, a second input for receiving a reference voltage, and is coupled to a transistor for providing a clamped voltage (VDDR) from the power supply node.

2. The clamp circuit of claim 1 wherein the dynamic clamp comprises a capacitor divider circuit.

3. The clamp circuit of claim 2 wherein the dynamic clamp comprises a resistor coupled to the capacitor divider circuit.

4. The clamp circuit of claim 2 wherein the dynamic clamp comprises a transistor coupled to the capacitor divider circuit.

5. The clamp circuit of claim 4 wherein the transistor within the dynamic clamp comprises an N-channel transistor.

6. The clamp circuit of claim 1 wherein the differential amplifier comprises an operational amplifier.

7. The clamp circuit of claim 1 wherein the differential amplifier comprises a comparator.

8. The clamp circuit of claim 1 wherein the transistor comprises a P-channel transistor.

9. The clamp circuit of claim 8 wherein the clamped VDDR voltage is provided at a source of the P-channel transistor.