Semiconductor memory device

• US 8,665,657 B2
• Filed: 09/27/2012
• Issued: 03/04/2014
• Est. Priority Date: 05/17/2010
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Koike, Tsuyoshi, Nakai, Youji
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/628,574
• Publication Number:
  US 20130028032A1
• Time in Patent Office: 523 Days
• Field of Search: 365/189.16
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines.

Claims

1. A semiconductor memory device, comprising:

a plurality of memory cells;

a pair of first and second local bit lines to which the plurality of memory cells are connected;

a pair of first and second write global bit lines;

a pair of first and second read global bit lines;

a first write transistor having a source connected to a power supply node to which a power supply voltage is supplied, a drain connected to the first local bit line, and a gate connected to the second write global bit line;

a second write transistor having a source connected to the power supply node, a drain connected to the second local bit line, and a gate connected to the first write global bit line;

a third write transistor having a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate to which a first control signal is supplied;

a fourth write transistor having a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate to which the first control signal is supplied;

a precharge circuit connected to the first and second local bit lines;

a write driver configured to control the first and second write global bit lines; and

a read circuit connected to the first and second local bit lines and the first and second read global bit lines.

2. The semiconductor memory device of claim 1, wherein

the read circuit includes:

a control transistor having a source connected to the power supply node, a drain connected to a power supply control node, and a gate to which the first control signal is supplied;

a first read transistor having a source connected to the power supply control node, a drain connected to the first read global bit line, and a gate connected to the first local bit line; and

a second read transistor having a source connected to the power supply control node, a drain connected to the second read global bit line, and a gate connected to the second local bit line.

3. The semiconductor memory device of claim 2, wherein

the precharge circuit precharges the first and second local bit lines in a precharge operation and releases the precharging of the first and second local bit lines in a write operation and a read operation,

the first control signal is a signal for turning off the third and fourth write transistors and turning on the control transistor in the precharge operation and the read operation, and turning on the third and fourth write transistors and turning off the control transistor in the write operation, and

the write driver sets the voltage levels of the first and second write global bit lines so that the first and second write transistors be off in the precharge operation and the read operation, and sets the voltage levels of the first and second write global bit lines according to write data so that either the first or second write transistor be on in the write operation.

4. The semiconductor memory device of claim 1, wherein

the read circuit includes:

a first read transistor having a source connected to the first write global bit line, a drain connected to the first read global bit line, and a gate connected to the first local bit line; and

a second read transistor having a source connected to the second write global bit line, a drain connected to the second read global bit line, and a gate connected to the second local bit line.

5. The semiconductor memory device of claim 4, wherein

the precharge circuit precharges the first and second local bit lines in a precharge operation and releases the precharging of the first and second local bit lines in a write operation and a read operation,

the first control signal is a signal for turning off the third and fourth write transistors in the precharge operation and the read operation, and turning on the third and fourth write transistors in the write operation, and

the write driver sets the voltage levels of the first and second write global bit lines so that the first and second write transistors be off in the precharge operation and the read operation, and sets the voltage levels of the first and second write global bit lines according to write data so that either the first or second write transistor be on in the write operation.

11. The semiconductor memory device of claim 1, wherein

the memory cells are two-port-read memory cells.

6. A semiconductor memory device, comprising:

a plurality of memory cells;

a pair of first and second local bit lines to which the plurality of memory cells are connected;

a pair of first and second write global bit lines;

a pair of first and second read global bit lines;

a first write transistor having a source connected to a power supply node to which a power supply voltage is supplied, a drain connected to the first local bit line, and a gate connected to the second write global bit line;

a second write transistor having a source connected to the power supply node, a drain connected to the second local bit line, and a gate connected to the first write global bit line;

a third write transistor having a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate to which a first control signal is supplied;

a fourth write transistor having a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate to which the first control signal is supplied;

a write driver configured to control the first and second write global bit lines and having a function of turning on or off the first and second write transistors simultaneously; and

a read circuit connected to the first and second local bit lines and the first and second read global bit lines.

7. The semiconductor memory device of claim 6, wherein

the read circuit includes:

a first read transistor having a source connected to the first write global bit line, a drain connected to the first read global bit line, and a gate connected to the first local bit line; and

a second read transistor having a source connected to the second write global bit line, a drain connected to the second read global bit line, and a gate connected to the second local bit line.

8. The semiconductor memory device of claim 7, wherein

the first control signal is a signal for turning off the third and fourth write transistors in the precharge operation and the read operation, and turning on the third and fourth write transistors in the write operation, and

the write driver sets the voltage levels of the first and second write global bit lines so that the first and second write transistors be on in the precharge operation, sets the voltage levels of the first and second write global bit lines so that the first and second write transistors be off in the read operation, and sets the voltage levels of the first and second write global bit lines according to write data so that either the first or second write transistor be on in the write operation.

12. The semiconductor memory device of claim 6, wherein

the memory cells are two-port-read memory cells.

9. A semiconductor memory device, comprising:

a plurality of memory cells;

a pair of first and second local bit lines to which the plurality of memory cells are connected;

a pair of first and second write global bit lines;

a pair of first and second read global bit lines;

a first write transistor having a source connected to a ground node to which a ground voltage is supplied, a drain connected to the first local bit line, and a gate connected to the second write global bit line;

a second write transistor having a source connected to the ground node, a drain connected to the second local bit line, and a gate connected to the first write global bit line;

a third write transistor having a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate to which a first control signal is supplied;

a fourth write transistor having a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate to which the first control signal is supplied;

a precharge circuit connected to the first and second local bit lines;

a write driver configured to control the first and second write global bit lines; and

a read circuit connected to the first and second local bit lines and the first and second read global bit lines.

10. The semiconductor memory device of claim 9, wherein

the read circuit includes:

a control transistor having a source connected to the power supply node, a drain connected to a power supply control node, and a gate to which the first control signal is supplied;

a first read transistor having a source connected to the power supply control node, a drain connected to the first read global bit line, and a gate connected to the first local bit line; and

a second read transistor having a source connected to the power supply control node, a drain connected to the second read global bit line, and a gate connected to the second local bit line.

13. The semiconductor memory device of claim 9, wherein

the memory cells are two-port-read memory cells.