Semiconductor memory device, memory system including the same, and method for adjusting timing between internal clock and command

• US 8,665,664 B2
• Filed: 07/09/2010
• Issued: 03/04/2014
• Est. Priority Date: 02/25/2010
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Moon, Jinyeong, Yoon, Sang-Sic
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Huang, Min
• Application Number:
  US12/833,048
• Publication Number:
  US 20110205818A1
• Time in Patent Office: 1,334 Days
• Field of Search: 365/233.1
• US Class Current: 365/233.11
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A method for adjusting a timing between an internal clock and a command in a gear down mode of a memory device includes detecting a sync pulse at rising and falling edges of the internal clock, and adjusting between the internal clock of the memory device and the command according to the detection result.

Claims

1. A semiconductor memory device, comprising:

a detection unit configured to detect a sync pulse at all of rising and falling edges of an internal clock within a single pulse width of the sync pulse, wherein the single pulse width of the sync pulse corresponds to one cycle of the internal clock used in a gear down mode; and

a transfer unit configured to transfer the detection result of the detection unit to a memory controller,

wherein the transfer unit comprises;

an operation section configured to perform a logic operation on the detection result of the detection unit,

wherein the operation section is configured to generate the operation result which contains information that current internal clock is available if the activation of the sync pulse is detected at the rising edge of the internal clock, and to generate the operation result to delay a command if the activation of the sync pulse is not detected at the rising edge of the internal clock and detected at the falling edge of the internal clock.

2. The semiconductor memory device of claim 1, wherein the transfer unit further comprises:

an output section configured to output the operation result of the operation section to the memory controller.

3. The semiconductor memory device of claim 1, wherein the operation section is configured to generate the operation result which contains information indicating that the detection of the sync pulse is failed if the activation of the sync pulse is not detected at both the rising and falling edges of the internal clock.

12. The semiconductor memory device of claim 1, wherein the detection unit comprises a dual edge counter.

4. A memory system, comprising:

a memory device comprising a detection unit configured to detect a sync pulse at all of rising and falling edges of the internal clock within a single pulse width of the sync pulse, wherein the single pulse width of the sync pulse corresponds to one cycle of the internal clock used in a gear down mode , and a transfer unit configured to transfer a detection result of the detection unit; and

a memory controller configured to adjust a timing between an internal clock of the memory device and a command to be applied to the memory device, in response to the detection result transferred from the transfer unit of the memory device,

wherein the transfer unit comprises;

an operation section configured to perform a logic operation on the detection result of the detection unit,

wherein the operation section is configured to generate the operation result which contains information that current internal clock is available if the activation of the sync pulse is detected at the rising edge of the internal clock, and to generate the operation result, wherein the operation result is used to delay the command if the activation of the sync pulse is not detected at the rising edge of the internal clock and detected at the falling edge of the internal clock.

5. The memory system of claim 4, wherein the transfer unit further comprises:

an output section configured to output an operation result of the operation section to the memory controller.

6. The memory system of claim 4, wherein the operation section is configured to generate the operation result which contains information indicating that the detection of the sync pulse is failed if the activation of the sync pulse is not detected at both the rising and falling edges of the internal clock.

7. A semiconductor memory device, comprising:

a detection unit configured to detect a sync pulse at all of rising and falling edges of the internal clock within a single pulse width of the sync pulse, wherein the single pulse width of the sync pulse corresponds to one cycle of the internal clock used in a gear down mode; and

an internal clock adjusting unit configured to adjust a timing of the internal clock in response to a detection result of the detection unit,

wherein the internal clock adjusting unit comprises;

an operation section configured to perform a logic operation on the detection result of the detection unit,

wherein the operation section is configured to generate the operation result which contains information that current internal clock is available if the activation of the sync pulse is detected at the rising edge of the internal clock, and to generate the operation result, wherein the operation result is used to delay the command if the activation of the sync pulse is not detected at the rising edge of the internal clock and detected at the falling edge of the internal clock.

8. The semiconductor memory device of claim 7, wherein the internal clock adjusting unit further comprises:

an internal clock selection section configured to select the internal clock or an inverted internal clock according to the detection result of the operation section.

9. The semiconductor memory device of claim 8, wherein the operation section is configured to transfer information, which indicates that the current internal clock is available, to the internal clock selection section if the activation of the sync pulse is detected at the rising edge of the internal clock, and to transfer information, which instructs the internal clock selection section to use the inverted internal clock as a new internal clock, to the internal clock selection section if the activation of the sync pulse is not detected at the rising edge of the internal clock and detected at the falling edge of the internal clock.

10. The semiconductor memory device of claim 9, wherein the operation section is configured to generate information indicating that the detection of the sync pulse fails, if the activation of the sync pulse is not detected at both the rising and falling edge of the internal clock, wherein the semiconductor memory devices further comprises an output unit configured to output the information to a memory controller.

11. The semiconductor memory device of claim 10, wherein the sync pulse is applied to the memory device via a pad through which a chip select signal is inputted.

13. The semiconductor memory device of claim 7, wherein the detection unit comprises a dual edge counter.