Phase detector for bursty data streams

• US 8,666,010 B1
• Filed: 09/24/2012
• Issued: 03/04/2014
• Est. Priority Date: 09/24/2012
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Novellini, Paolo
• Primary Examiner(s): HA, DAC V
• Application Number:
  US13/625,100
• Time in Patent Office: 526 Days
• Field of Search: 375/371, 375/373, 375/375, 375/376, 327/147, 327/150, 327/152, 327/154, 327/155, 327/156, 327/159
• US Class Current: 375/371
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A bursty phase detector comprises upper and lower branches. The upper branch includes a voltage-controlled oscillator (VCO) providing a VCO phase; a phase detector with a first input for receiving a data stream and a second input coupled to the output of the VCO, the phase detector providing a phase error; a sample selector with a first input for receiving a sum of the VCO phase and the phase error, and a second input coupled to receive the data stream, the sample selector providing a data stream sample; a signal stream detector with a first input for receiving the sum of the VCO phase and the phase error, and a second input coupled to the output of the sample selector, the signal stream detector generating a data stream phase and a data stream detect signal. The lower branch includes a delay component with an input for receiving the data stream.

Claims

1. A bursty phase detector for processing a data stream, comprising:

an upper branch, including;

a voltage-controlled oscillator (VCO) configured to provide a VCO phase at an output of the VCO;

a phase detector with a first input coupled to receive the data stream and a second input coupled to the output of the VCO, the phase detector configured to provide a phase error at its output;

a sample selector with a first input coupled to receive a sum of the VCO phase and the phase error, and a second input coupled to receive the data stream, the sample selector configured to provide a data stream sample at its output; and

a data stream detector with a first input coupled to receive the sum of the VCO phase and the phase error, and a second input coupled to the output of the sample selector, the data stream detector configured to generate a data stream phase and a data stream detect signal; and

a lower branch, including a delay component with an input coupled to receive the data stream.

2. The bursty phase detector of claim 1, wherein the data stream comprises a preamble segment and a data segment.

3. The bursty phase detector of claim 2, wherein the preamble segment is for triggering the data stream detect signal.

4. The bursty phase detector of claim 1, wherein the VCO has an input coupled to a fixed control signal.

5. The bursty phase detector of claim 1, wherein the phase detector is configured to provide the phase error by comparing a phase of the data stream to the VCO phase.

6. The bursty phase detector of claim 1, further comprising an adder for generating the sum of the VCO phase and the phase error.

7. The bursty phase detector of claim 1, wherein the sum of the VCO phase and the phase error carries a runtime phase of the data stream.

8. The bursty phase detector of claim 1, wherein the delay component is configured to store the data stream for a time period greater than, or equal to, a processing time for generating the data stream phase and the data stream detect signal.

9. The bursty phase detector of claim 1, wherein the data stream detect signal provides an indication of a start of the data stream.

10. A receiver for processing a data stream, comprising:

a bursty phase detector including an upper branch and a lower branch;

wherein the upper branch comprises;

a first voltage-controlled oscillator (VCO) configured to provide a first VCO phase at an output of the VCO;

a first phase detector with a first input coupled to receive the data stream, and a second input coupled to the output of the first VCO, the first phase detector configured to provide a first phase error at its output;

a sample selector with a first input coupled to receive a sum of the first VCO phase and the first phase error, and a second input coupled to receive the data stream, the sample selector configured to provide a data stream sample at its output; and

a signal stream detector with a first input coupled to receive the sum of the first VCO phase and the first phase error, and a second input coupled to the output of the sample selector, the signal stream detector configured to generate a data stream phase and a data stream detect signal;

wherein the lower branch comprises a delay component with an input coupled to receive the data stream;

a phase locked loop (PLL) coupled to receive an output of the delay element, the data stream phase, and the data stream detect signal, the PLL configured to provide a second VCO phase at an output of the PLL; and

a data sample selector with a first input coupled to the output of the delay component, and a second input coupled to the output of the PLL.

11. The receiver of claim 10, wherein the data stream comprises a preamble segment and a data segment.

12. The receiver of claim 10, further comprising an adder for generating the sum of the first VCO phase and the first phase error.

13. The receiver of claim 10, wherein the delay component is configured to store the data stream for a time period greater than, or equal to, a processing time for generating the data stream phase and the data stream detect signal.

14. The receiver of claim 10, wherein the PLL comprises:

a low-pass filter;

a second VCO with a first input coupled to an output of the low-pass filter, a second input coupled to receive the data stream phase, and a third input coupled to receive the data stream detect signal;

wherein the second VCO is configured to provide a second VCO phase at its output; and

a second phase detector with a first input coupled to the output of the delay component, a second input coupled to the output of the second VCO, and an output coupled to the low-pass filter.

15. The receiver of claim 14, wherein the second phase detector is configured to receive the data stream from the delay component after the second VCO phase is aligned with a phase of the data stream.

16. The receiver of claim 14, wherein the second VCO comprises:

an adder coupled to the output of the low-pass filter and further coupled to receive a center frequency signal;

a multiplexer with a first input coupled to receive the data stream phase, a second input coupled to an output of the adder, and a control input coupled to receive the data stream detect signal; and

an n-bit register with an input coupled to an output of the multiplexer, and an output coupled to an input of the adder.

17. The receiver of claim 16, wherein the multiplexer is configured to select the data stream phase upon receipt of the data stream detect signal.

18. The receiver of claim 14, wherein the low-pass filter is configured to remove local noise associated with the output of the second phase detector.

19. The receiver of claim 14, wherein the second VCO phase provided at the output of the second VCO is aligned with a phase of the data stream using the data stream phase generated by the signal stream detector.

20. The receiver of claim 10, wherein the data stream detect signal provides an indication of a start of the data stream.