High speed digital transient waveform detection system and method for use in an intelligent electronic device

• US 8,666,688 B2
• Filed: 03/13/2008
• Issued: 03/04/2014
• Est. Priority Date: 01/27/2005
• Status: Active Grant

• Current Assignee: EI Electronics LLC (Hubbell, Inc.)
• Original Assignee: Electro Industries/Gaugetech
• Inventors: Spanier, Joseph, Zhu, Hai, Wang, Wei
• Primary Examiner(s): COSIMANO, EDWARD R
• Application Number:
  US12/075,747
• Publication Number:
  US 20080215264A1
• Time in Patent Office: 2,182 Days
• Field of Search: 734/321, 738/658, 738/663, 324/72, 324/76.11, 324/76.12, 324/76.38, 324/102, 340/500, 340/540, 340/635, 340/657, 340/659, 340/660, 340/664, 340/870.01, 340/870.07, 702/1, 702/57, 702/64, 702/65, 702/66, 702/69, 702/79, 702/127, 702/187, 702/189, 708/100, 708/105, 708/131, 708/160, 708/200, 708/201, 708/207
• US Class Current: 702/69
• CPC Class Codes: G01R 1/40 Modifications of instruments to indicate the maximum or the minimum value reached in a time interval, e.g. by maximum indicator pointer
• CPC Class Codes: G01R 19/04 Measuring peak values or amplitude or envelope of ac or of pulses
• CPC Class Codes: G01R 19/2509 Details concerning sampling, digitizing or waveform capturing
• CPC Class Codes: G01R 19/2513 Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging
• CPC Class Codes: G01R 29/02 Measuring characteristics of individual pulses, e.g. deviation from pulse flatness, rise time or duration
• CPC Class Codes: G06F 11/30 Monitoring
• CPC Class Codes: G06F 17/40 Data acquisition and logging for input to computer G06F3/00
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass

Abstract

A system and a method is provided for the detection and capture, and in particular for an ultra high speed detection and capture, of transients in input voltages by an intelligent electronic device. The system and method detects transients for input voltages in either phase to phase or phase to neutral measurements and permits a user to set threshold levels for detecting transients in input voltages. In an embodiment, the system and method further provides a field programmable gate array as a controller for managing transient detection. The field programmable gate array includes a state machine for determining the state of the sampled signal with respect to a threshold level at a specified waveform sample period.

Claims

1. An intelligent electronic device (IED) for detecting at least one transient waveform comprising:

i) at least one analog-to-digital converter circuit configured to sample at least one analog voltage channel to detect and output digital samples of voltage transients in each of a plurality of sequential waveform sample periods;

ii) a waveform capture circuit configured to sample said at least one analog voltage channel and output digital samples of said at least one analog voltage channel in each of said plurality of sequential waveform sample periods; and

iii) a field programmable gate array (FPGA) configured to receive the digital samples of said voltage transients output from the at least one analog-to-digital converter circuit in each of the plurality of waveform sample periods, and detect and store a single peak transient value and its associated duration value in each of said plurality of waveform sample periods.

2. The IED of claim 1, wherein the analog-to-digital converter circuit samples the at least one analog voltage channel at a sampling rate above 1 Mhz to detect and output said digita samples of said voltage transients.

3. The IED of claim 1, wherein the at least one analog-to-digital converter circuit samples the at least one analog voltage channel at a sampling rate substantially in the range from 1 MHz to 50 MHz.

4. The IED of claim 1, wherein the FPGA further comprises a dual port memory.

5. The IED of claim 1, further comprising at least one processor configured to produce merged data by correlating said peak transient value and its associated duration value in each waveform sample period with the sampled waveform data in each waveform sample period and replacing at least one digital sample of said at least one analog voltage channel with said peak transient value.

6. The IED of claim 1, wherein the FPGA is further configured to receive the digital samples of voltage transient values output from the at least one analog-to-digital converter circuit in each waveform sample period, transfer the digital samples to at least one processor at the end of each waveform sample period, and transfer the detected single peak transient value and its associated duration value to the at least one processor.

7. The IED of claim 1 further comprising an Ethernet communication module capable of sending data via HTTP protocol.

8. The IED of claim 1, further comprising a communication device to provide emails out to a user upon events occurring.

9. The IED of claim 1, further comprising a memory for storing said waveform data samples of the at least one analog voltage channel in each waveform sample period.

10. The IED of claim 1, further comprising a web server for communicating the transient data to an external device.

11. The IED of claim 1, wherein the at least one analog-to-digital converter and the FPGA are disposed in a socket-type meter form.

12. The IED of claim 1, wherein the at least one analog-to-digital converter and the FPGA are disposed in a panel mounted meter form.

13. The IED of claim 1, wherein the at least one analog-to-digital converter and the FPGA are disposed in a switchboard meter form.

14. The IED of claim 1, wherein the at least one analog-to-digital converter and the FPGA are disposed in a A-base front wired meter form.

15. The IED of claim 1, wherein the at least one analog-to-digital converter and the FPGA are disposed in a circuit breaker mounted meter form.

16. The IED of claim 1, further comprising a touchscreen display configured to display data and receive input commands.

17. The IED of claim 1, further comprising a communication device configured to couple the IED to a network, wherein the communication device operates on a wireless protocol.

18. The IED of claim 1, wherein the FPGA is configured via firmware.

19. The IED of claim 1, further comprising at least one processor configured to produce merged waveform data in each of said plurality of waveform sample periods by combining said single detected peak transient value and associated duration value of the at least one analog voltage channel together with said digital samples of said at least one analog voltage channel waveform data.

20. The IED of claim 19 wherein the at least one processor is configured to generate and transmit threshold voltage levels to the FPGA to allow the FPGA to detect said single detected peak transient value from the at least one analog voltage channel in each of said waveform sample periods.

21. The lED of claim 1, further comprising a transient detection system including:

a multiplexer/subtractor circuit configured to receive the digital samples from the at least one sampled analog voltage channel;

a threshold comparator for detecting whether a digital sample is above a pre-determined transient threshold level;

a first state machine configured to control a process of selecting peak transient values in each waveform sample period;

a duration counter for measuring a duration of a detected transient;

a peak comparator for detecting the peak value of the digital samples that may occur in each of said plurality of waveform sample periods;

a transient capture memory for storing output digital samples of said at least one analog voltage channel in each of said plurality of sequential waveform sample periods; and

a transient clock programmed by the FPGA to clock a peak latch.

22. The IED of claim 21, wherein the multiplexer/subtractor circuit is configured to operate in one of a phase to phase voltage mode or a phase to neutral voltage mode.

23. The IED of claim 21, wherein the transient capture memory is one of an internal transient capture memory contained within the FPGA or an external transient capture memory not contained within the FPGA.

24. The IED of claim 21, further comprising an intermediate holding register for temporarily holding parameter values collected during each of said plurality of waveform sample periods.

25. The IED of claim 24, wherein the parameter values comprise:

(a) a peak transient value, (b) a continuation value for indicating that a transient value remained above the pre-determined threshold when crossing over from one waveform sample period to an adjoining waveform sample period, (c) a new transient value N for indicating that the transient was not a carryover from a previous waveform sample period and (d) a duration value indicating a duration of the peak transient value.

26. A method for detecting transients in an input analog voltage waveform, the method comprising:

a) receiving a plurality of transient samples from said input analog voltage waveform in successive waveform sample periods;

b) determining if the currently received transient sample is greater than previously latched input transient sample in each of said waveform sample periods;

c) overwriting the previously latched input transient sample with the current transient sample in the case where said determining step is satisfied in each of said waveform sample periods; and

d) identifying a peak transient sample corresponding to the currently latched input transient sample at the end of each of said waveform sample periods.

27. The method according to claim 26, further comprising:

taking the absolute value of the current transient sample prior to said step (b).

28. The method according to claim 26, further comprising:

determining an associated duration for each latched input transient sample, and

storing the duration value in a duration counter.

29. An intelligent electronic device (lED) comprising:

first means for sampling at least one analog voltage channel in each of a plurality of sequential waveform sample periods at a first sampling rate and for outputting first digital samples;

second means for sampling the at least one analog voftage channel in each of a plurality of sequential waveform sample periods at a second sampling rate and for outputting second digital samples, the first sampling rate being faster than the first sampling rate;

means for detecting a peak transient value and its associated duration value of the first digital samples; and

means for combining said peak transient value and its associated duration value with the second digftal samples for a common at least one waveform sample period.

30. An intelligent electronic device (IED) comprising:

at least one analog to digital converter configured to sample at least one AC line voltage signal, and

at least one field programmable gate array (FPGA) configured to receive samples from said at least one analog to digital converter wherein said FPGA operates as a state machine.

31. The IED of claim 30, wherein the FPGA is an at least one processor executing code.

32. The IED of claim 30, wherein the FPGA further includes a comparator function for comparing transient values and a latch function for storing peak transient values.

33. The IED of claim 30, wherein the analog to digital converter circuit samples the at least one AC line voltage signal at a sampling rate above 1 Mhz.

34. The IED of claim 30, wherein the at least one analog to digital converter circuit samples the at least one AC line voltage signal at a sampling rate substantially in the range from 1 MHz to 50 MHz.

35. The IED of claim 30, wherein the at least one FPGA further comprises a dual port memory.

36. The IED of claim 30, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a socket-type meter form.

37. The IED of claim 30, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a panel mounted meter form.

38. The IED of claim 30, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a switchboard meter form.

39. The IED of claim 30, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a A-base front wired meter form.

40. The IED of claim 30, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a circuit breaker mounted meter form.

41. The IED of claim 30, further comprising a touchscreen display configured to display data and receive input commands.

42. The IED of claim 30, further comprising a communication device configured to couple the lED to a network, wherein the communication device operates on a wireless protocol.

43. The IED of claim 30, wherein the at least one FPGA is configured via firmware.

44. The IED of claim 30, wherein the FPGA state machine determines a peak of a transient signal by utilizing logic incorporated by the state machine.

45. The IED of claim 44, wherein the FPGA state machine determines a duration of the transient event.

46. The IED of claim 44, wherein the FPGA sends said one or more samples to a processor.

47. The IED of claim 46, wherein the processor determines a duration of the transient event.

48. An intelligent electronic device (IED) comprising:

at least one analog to digital converter configured to sample at least one AC line voltage signal,

at least one field programmable gate array (FPGA) configured to receive samples from said at least one analog to digital converter wherein said FPGA operates as a state machine,

at non-volatile mass memory for storing long term historical data,

a graphical LCD display,

an Ethernet connection utilizing at least one protocol, and

at least one processor configured to store sample data generated from said at least one analog to digital converter in said mass memory and transfer said sample data to a central computer.

49. The IED of claim 48, wherein said Ethernet connection is further operative to email to a user when a power quality event occurs.

50. The IED of claim 48, wherein the analog to digital converter circuit samples the at least one AC line voltage signal at a sampling rate above 1 Mhz.

51. The IED of claim 48, wherein the at least one analog to digital converter circuit samples the at least one AC line voltage signal at a sampling rate substantially in the range from 1 MHz to 50 MHz.

52. The IED of claim 48, wherein the at least one FPGA further comprises a dual port memory.

53. The IED of claim 48, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a socket-type meter form.

54. The IED of claim 48, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a panel mounted meter form.

55. The IED of claim 48, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a switchboard meter form.

56. The IED of claim 48, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a A-base front wired meter form.

57. The IED of claim 48, wherein the at least one analog to digital converter and the at least one FPGA are disposed in a circuit breaker mounted meter form.

58. The IED of claim 48, wherein the display is a touchscreen display configured to display data and receive input commands.

59. The IED of claim 48, further comprising a communication device configured to couple the ED to a network, wherein the communication device operates on a wireless protocol.

60. The IED of claim 48, wherein the at least one FPGA is configured via firmware.

61. The IED of claim 48, wherein the FPGA determines a magnitude of a voltage transient event from samples generated from the at least one analog to digital converter.

62. The IED of claim 61, wherein the FPGA determines a duration of said voltage transient event.

63. The IED of claim 61, wherein the FPGA incorporates a comparator.

64. The IED of claim 61, wherein the FPGA incorporates a latch.

65. An intelligent electronic device (IED) comprising:

at least one analog to digital converter configured to sample at least one AC line voltage signal, and

at least one field programmable gate array (FPGA) configured to receive samples from said at least one analog to digital converter wherein said FPGA operates as a state machine to determine a peak value and duration of a transient event occurring in the at least one AC line voltage signal by utilizing logic incorporated by the state machine.

66. The IED of claim 65, further comprising input/output (I/O) interface for communicating the determined energy usage data to an external device via a pulse output.

67. The IED of claim 65, further comprising a communication device to provide emails out to a user upon events occurring.

68. The IED of claim 65, wherein the at least one analog to digital converter and at least one FPGA are disposed in a socket-type meter form.

69. The IED of claim 65, wherein the at least one analog to digital converter and at least one FPGA are disposed in a panel mounted meter form.

70. The IED of claim 65, wherein the at least one analog to digital converter and at least one FPGA are disposed in a switchboard meter form.

71. The IED of claim 65, wherein the at least one analog to digital converter and at least one FPGA are disposed in a A-base front wired meter form.

72. The IED of claim 65, wherein the at least one analog to digital converter and at least one FPGA are disposed in a circuit breaker mounted meter form.

73. The IED of claim 65, wherein the analog to digital converter circuit samples the at least one AC line voltage signal at a sampling rate above 1 Mhz.

74. The IED of claim 65, wherein the at least one analog to digital converter circuit samples the at least one AC line voltage signal at a sampling rate substantially in the range from 1 MHz to 50 MHz.

75. The IED of claim 65, wherein the at least one FPGA further comprises a dual port memory.

76. The IED of claim 65, further comprising a touchscreen display configured to display data and receive input commands.

77. The IED of claim 65, further comprising a communication device configured to couple the lED to a network, wherein the communication device operates on a wireless protocol.

78. The IED of claim 65, wherein the at least one FPGA is configured via firmware.

79. The IED of claim 65, wherein:

a first of the at least one analog to digital converter samples the at least one AC line voltage signal in each of a plurality of sequential waveform sample periods at a first sampling rate and for outputting first digital samples, and

a second of the at least one analog to digital converter samples the at least one AC line voltage signal in each of a plurality of sequential waveform sample periods at a second sampling rate and for outputting second digital samples, the first sampling rate being faster than the first sampling rate.

80. The IED of claim 79, wherein the FPGA detects the peak transient value and its associated duration value from the first digital samples.

81. The IED of claim 80, further comprising at least one processing device that combines the peak transient value and its associated duration value with the second digital samples for a common at least one waveform sample period to produce merge waveform data.

82. The IED of claim 65, further comprising at least one processing device configured to determine energy usage data from the sampled at least one AC line voltage signal and a display for displaying the determined energy usage data.

83. The IED of claim 82, further comprising a web server for communicating the determined energy usage data to an external device.

84. The IED of claim 82, further comprising a communication device for communicating the determined energy usage data to an external device via a communication protocol.

85. The IED of claim 84, wherein the communication protocol is an Ethernet protocol.