System including a fine-grained memory and a less-fine-grained memory

• US 8,667,212 B2
• Filed: 08/13/2012
• Issued: 03/04/2014
• Est. Priority Date: 05/30/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: McWilliams, Thomas M., Cohen, Earl T., Bodwin, James M., Bruening, Ulrich
• Primary Examiner(s): Bragdon, Reginald
• Assistant Examiner(s): Faal, Baboucarr
• Application Number:
  US13/584,755
• Publication Number:
  US 20120311246A1
• Time in Patent Office: 568 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0284 Multiple user address space allocation, e.g. using different base addresses interprocessor communication G06F15/163
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.

Claims

1. A method comprising:

coalescing a first one of a plurality of logical partitions stored in a first one of a plurality of pages of a non-volatile, less-fine-grained memory and a second one of the plurality of logical partitions stored in a second one of the plurality of pages of the less-fine-grained memory into separate regions in a particular page of a write buffer in a volatile, fine-grained memory, wherein each of the plurality of pages of the less-fine-grained memory is enabled to store a respective two or more of the plurality of logical partitions, and wherein a minimum writable unit of the less-fine-grained memory is one of the plurality of pages of the less-fine-grained memory;

writing, subsequent to the coalescing, the particular page of the write buffer to a third one of the plurality of pages of the less-fine-grained memory, wherein the first page, the second page, and the third page are all different ones of the plurality of pages of the less-fine-grained memory; and

maintaining a map comprising a plurality of entries, each of the plurality of entries associating a respective one of a plurality of elements with a respective one of the plurality of logical partitions of a respective one of the plurality of pages of the less-fine-grained memory, and wherein prior to the writing, a first one of the plurality of elements is associated with the first logical partition via a first one of the plurality of entries of the map, and a second one of the plurality of elements is associated with the second logical partition via a second one of the plurality of entries of the map.

2. The method of claim 1, wherein the less-fine-grained memory is a solid-state memory.

3. The method of claim 1, wherein a size of the first logical partition is different from a size of the second logical partition.

4. The method of claim 1, wherein the maintaining comprises updating the first entry to associate the first element with a third one of the plurality of logical partitions stored in the third page of the less-fine-grained memory.

5. The method of claim 4, wherein the updating the first entry comprises updating an offset stored in the first entry to be an offset of the third logical partition stored in the third page of the less-fine-grained memory.

6. The method of claim 5,

wherein prior to the updating the first entry, the offset stored in the first entry is an offset of the first logical partition stored in the first page of the less-fine-grained memory;

and

wherein the offset of the third logical partition is different from the offset of the first logical partition.

7. The method of claim 5, wherein the offset stored in the first entry has a granularity of no more than 64 bytes.

8. The method of claim 5, wherein the offset stored in the first entry has a granularity of no more than eight bytes.

9. The method of claim 4, further comprising:

reading, prior to the coalescing, the first element from the first page of the less-fine-grained memory; and

reading, subsequent to the writing, the first element from the third page of the less-fine-grained memory.

10. The method of claim 4,

wherein each of the first logical partition, the second logical partition, and the third logical partition stores a respective error detecting code;

and

wherein the writing comprises storing in the third page of the less-fine-grained memory a respective error correcting code protecting contents of the third page of the less-fine-grained memory including the third logical partition, and wherein the respective error correcting code of the third page of the less-fine-grained memory is different from the respective error detecting code of the third logical partition.

11. The method of claim 1, wherein the particular page of the write buffer is one of a plurality of pages of the write buffer.

12. The method of claim 1, wherein the first logical partition stores data of the first element in a compressed form.

13. The method of claim 12, wherein the first logical partition further stores a header of the compressed data of the first element.

14. The method of claim 13, wherein the header comprises a type of compression used to produce the compressed form.

15. The method of claim 13, wherein the header comprises a size of the compressed data of the first element.

16. The method of claim 1, wherein the coalescing comprises storing at least a portion of the first logical partition into the particular page of the write buffer, and subsequently storing at least a portion of the second logical partition into the particular page of the write buffer.

17. The method of claim 16, wherein the coalescing further comprises:

computing a respective error detecting code for each of the at least a portion of the first logical partition and the at least a portion of the second logical partition; and

storing the respective error detecting codes into the particular page of the write buffer.

18. The method of claim 16,

wherein the first logical partition comprises a respective error detecting code;

and

wherein the at least a portion of the first logical partition is all of the first logical partition.

19. The method of claim 1, wherein, prior to the coalescing, the first page of the less-fine-grained memory stores at least two of the plurality of logical partitions.

20. The method of claim 1, further comprising, subsequent to the coalescing, erasing a block of the less-fine-grained memory containing the first page of the less-fine-grained memory.

21. The method of claim 20, further comprising, subsequent to the erasing, adding the block to a free list.

22. The method of claim 21, further comprising determining the third page of the less-fine-grained memory based, at least in part, on the free list.

23. The method of claim 1, further comprising, in event of a power disruption of a primary power source coupled to the fine-grained memory, powering the write buffer via a back-up power source.

24. The method of claim 23, further comprising, in the event of the power disruption being subsequent to the coalescing and prior to the writing, saving the particular page of the write buffer to a determined one of the plurality of pages of the less-fine-grained memory.

25. The method of claim 24, wherein the determined page of the less-fine-grained memory is the third page of the less-fine-grained memory.