Method and apparatus for processing data in an embedded system
First Claim
Patent Images
1. A device, comprising:
- a processor;
a core memory having a receive buffer and a transmit buffer;
a bus coupled to the processor and the core memory;
at least one co-processor separate from the core memory and coupled to the core memory via a direct link that is accessible only by the at least one co-processor and by the core memory, wherein the at least one co-processor accesses at least one of;
the receive buffer of the core memory, or the transmit buffer of the core memory, without assistance from the processor; and
at least one network interface providing a direct path between the core memory and a network;
wherein;
the receive buffer has a plurality of portions and the transmit buffer has a plurality of portions;
a first one of the portions of the receive buffer and a first one of the portions of the transmit buffer are dedicated to network and bus access;
a second one of the portions of the receive buffer and a second one of the portions of the transmit buffer are dedicated to co-processor and bus access; and
a third one of the portions of the receive buffer and a third one of the portions of the transmit buffer are dedicated to network and co-processor access.
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Abstract
In one embodiment, a network device is disclosed. For example, in one embodiment of the present invention, the device comprises a processor and a core memory having a receive buffer and a transmit buffer. The device comprises a bus coupled to the processor and the core memory. The device comprises at least one co-processor coupled to the core memory via a direct link, wherein the at least one co-processor is capable of accessing at least one of: the receive buffer, or the transmit buffer, without assistance from the processor.
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Citations
18 Claims
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1. A device, comprising:
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a processor; a core memory having a receive buffer and a transmit buffer; a bus coupled to the processor and the core memory; at least one co-processor separate from the core memory and coupled to the core memory via a direct link that is accessible only by the at least one co-processor and by the core memory, wherein the at least one co-processor accesses at least one of;
the receive buffer of the core memory, or the transmit buffer of the core memory, without assistance from the processor; andat least one network interface providing a direct path between the core memory and a network; wherein; the receive buffer has a plurality of portions and the transmit buffer has a plurality of portions; a first one of the portions of the receive buffer and a first one of the portions of the transmit buffer are dedicated to network and bus access; a second one of the portions of the receive buffer and a second one of the portions of the transmit buffer are dedicated to co-processor and bus access; and a third one of the portions of the receive buffer and a third one of the portions of the transmit buffer are dedicated to network and co-processor access. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for accessing data stored in a core memory having a receive buffer and a transmit buffer, comprising:
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dividing the receive buffer into a plurality of portions and the transmit buffer into a plurality of portions; dedicating access to a first one of the portions of the receive buffer and a first one of the portions of the transmit buffer to at least one network interface and to a bus; dedicating access to a second one of the portions of the receive buffer and a second one of the portions of the transmit buffer to at least one co-processor and the bus; dedicating access to a third one of the portions of the receive buffer and a third one of the portions of the transmit buffer to the at least one network interface and the at least one co-processor; reading data from at least one of;
the receive buffer of the core memory or the transmit buffer of the core memory, by the at least one co-processor via a direct link, wherein the at least one co-processor is separate from the core memory, and wherein the core memory is coupled to the at least one network interface that provides a direct path between the core memory and a network;processing the data by the at least one co-processor to produce processed data; and writing the processed data to at least one of;
the receive buffer of the core memory or the transmit buffer of the core memory, by the at least one co-processor via the direct link that is accessible only by the at least one co-processor and by the core memory, wherein the at least one co-processor performs the reading and the writing without assistance from a processor that is coupled to the core memory via the bus. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A non-transitory computer-readable medium having stored thereon a plurality of instructions, the plurality of instructions including instructions which, when executed by a processor, cause the processor to perform a method for accessing data stored in a core memory having a receive buffer and a transmit buffer, comprising:
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dividing the receive buffer into a plurality of portions and the transmit buffer into a plurality of portions; dedicating access to a first one of the portions of the receive buffer and a first one of the portions of the transmit buffer to at least one network interface and to a bus; dedicating access to a second one of the portions of the receive buffer and a second one of the portions of the transmit buffer to at least one co-processor and the bus; dedicating access to a third one of the portions of the receive buffer and a third one of the portions of the transmit buffer to the at least one network interface and the at least one co-processor; reading data from at least one of;
the receive buffer of the core memory or the transmit buffer of the core memory, by the at least one co-processor via a direct link, wherein the at least one co-processor is separate from the core memory, and wherein the core memory is coupled to the at least one network interface that provides a direct path between the core memory and a network;processing the data by the at least one co-processor to produce processed data; and writing the processed data to at least one of;
the receive buffer of the core memory or the transmit buffer of the core memory, by the at least one co-processor via the direct link that is accessible only by the at least one co-processor and by the core memory, wherein the at least one co-processor performs the reading and the writing without assistance from a processor that is coupled to the core memory via the bus.
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18. A method for accessing data stored in a core memory having a receive buffer and a transmit buffer, comprising:
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dividing the receive buffer into a plurality of portions and the transmit buffer into a plurality of portions; dedicating access to a first one of the portions of the receive buffer and a first one of the portions of the transmit buffer to at least one network interface and to a bus; dedicating access to a second one of the portions of the receive buffer and a second one of the portions of the transmit buffer to a co-processor and the bus; dedicating access to a third one of the portions of the receive buffer and a third one of the portions of the transmit buffer to the at least one network interface and the co-processor; receiving a status signal by the co-processor from the core memory via a direct link that is accessible only by the co-processor and by the core memory, wherein the co-processor is separate from the core memory, and wherein the core memory is coupled to at least one network interface that provides a direct path between the core memory and a network; determining whether the core memory is available for access; and accessing the core memory directly by the co-processor if the core memory is deemed to be available for access.
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Specification