Apparatus and method for reducing power consumption in system on chip

• US 8,667,313 B2
• Filed: 09/10/2008
• Issued: 03/04/2014
• Est. Priority Date: 09/11/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sung-Min
• Primary Examiner(s): BUTLER, DENNIS
• Application Number:
  US12/733,599
• Publication Number:
  US 20100205468A1
• Time in Patent Office: 2,001 Days
• Field of Search: None
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

An apparatus and method for reducing power consumption in a System on Chip (SoC) are provided. The SoC includes a clock unit for providing clocks to all elements included in the SoC, a Central Processing Unit (CPU) for controlling the SoC to perform designated functions, a main regulator for supplying power provided from an external battery to remaining elements included in the SoC other than a PMU, and a restoration processor for storing, in the PMU, registration information on the CPU and all peripherals included in the SoC when a transition from an active state to a sleep state is made. The PMU stops provision of a clock from the CPU by controlling the clock unit for stopping provision of all clocks by controlling the clock unit and for controlling the main regulator to be powered off when the restoration processor, wherein the PMU requests the restoration processor to store the registration information, completes the register information storing, when the transition from the sleep state to the active state is made.

Claims

1. A System on Chip (SoC) configured to reduce power consumption, the SoC comprising:

a clock unit configured to provide clock signals to all elements included in the. SoC, the elements comprising a modem and one or more peripheral elements;

a main regulator configured to supply power provided from an external battery to remaining elements included in the SoC other than a Power Management Unit (PMU); and

processing circuitry configured to;

control the SoC to perform designated functions;

stop the clock signal to a CPU by controlling the clock unit when a transition from an active state to a sleep state is made;

store, in the PMU, register information associated with the CPU and all of the peripherals included in the SoC after the clock signal is stopped to the CPU;

when the storing of register information is completed, stop provision of all clock signals to all of the elements by controlling the clock unit and control the main regulator to be powered off when the transition from the active state to the sleep state is made;

control the main regulator to be powered on and provide the clock signal to the all of the peripherals other than the CPU when a transition from the sleep state to the active state is made;

restore all register information associated with the CPU and the all of the peripherals included in the SoC after the clock signal is provided to the all of the peripherals other than the CPU; and

when the restoring of the register information is completed, provide the clock signal to the CPU.

2. The SoC of claim 1, wherein the PMU comprises an auxiliary regulator configured to supply the PMU with power provided from the external battery.

3. The SoC of claim 2, wherein the auxiliary regulator is configured to supply power to the PMU in the active state and the sleep state.

4. The SoC of claim 2, wherein the auxiliary regulator is configured to have a lower operation current and power consumption than the main regulator.

5. The SoC of claim 1, wherein the SoC is configured in a Wireless Personal Area Network (WPAN).

6. The SoC of claim 1, wherein the clock unit, the main regulator, the processing circuitry, the PMU, and the one or more peripheral elements are all integrally formed in the SoC.

7. A method of reducing power consumption in an SoC, the method comprising:

stopping generation of a clock signal provided to a CPU by detecting a transition from an active state to a sleep state in a Power Management Unit (PMU);

storing register information of the CPU and peripherals included in the SoC after the clock signal is stopped to the CPU;

when the storing of register information is completed, stopping provision of all clock signals to all elements, the elements comprising a modem and one or more peripheral elements;

powering off a main regulator;

powering on the main regulator and providing clock signals to elements included in the SoC other than the CPU by detecting a transition from the sleep state to the active state;

restoring the stored register information of the CPU and the peripherals included in the SoC after the clock signal is provided to the all of the peripherals other than the CPU; and

providing the clock signal to the CPU, when the restoring of the register information is completed.

8. The method of claim 7, further comprising:

powering on an auxiliary regulator of the PMU when a battery is powered on in a battery-off state;

powering on the main regulator under the control of the PMU; and

providing clock signals to all elements included in the SoC.

9. The method of claim 7, wherein the PMU comprises an auxiliary regulator for supplying power to the PMU, the power being provided from an external battery.

10. The method of claim 9, wherein the auxiliary regulator supplies power to the PMU in an active state and a sleep state.

11. The method of claim 9, wherein the auxiliary regulator has a lower operation current and power consumption than the main regulator.

12. The method of claim 7, wherein the SoC is configured in a Wireless Personal Area Network (WPAN).

13. The method of claim 7, wherein the clock unit, the main regulator, the processing circuitry, the PMU, and the one or more peripheral elements are all integrally formed in the SoC.

14. A network element comprising:

a System on Chip (SoC) comprising;

a clock unit configured to provide clock signals to all elements included in the SoC, the elements comprising a modem and one or more peripheral elements;

a Central Processing Unit (CPU) coupled to a main regulator and configured to supply power to remaining elements included in the SoC other than a Power Management Unit (PMU); and

processing circuitry configured to;

control the SoC to perform designated functions;

stop the clock signal to the CPU by controlling the clock unit when a transition from an active state to a sleep state is made;

store, in the PMU, register information on the CPU and all of the peripherals included in the SoC after the clock signal is stopped to the CPU;

when the storing of register information is completed, stop provision of all clock signals to all of the elements by controlling the clock unit and control the main regulator to be powered off when the transition from the sleep state to the active state is made;

control the main regulator to be powered on and provide the clock signal to the all of the peripherals other than the CPU when a transition from the sleep state to the active state is made;

restore all register information of the CPU and the all of the peripherals included in the SoC after the clock signal is provided to the all of the peripherals other than the CPU; and

when the restoring of the register information is completed, provide the clock signal to the CPU.

15. The network element of claim 14, wherein the PMU comprises an auxiliary regulator configured to supply the PMU with power provided from the external battery.

16. The network element of claim 15, wherein the auxiliary regulator is configured to supply power to the PMU in the active state and the sleep state.

17. The network element of claim 15, wherein the auxiliary regulator is configured to have a lower operation current and power consumption than the main regulator.

18. The network element of claim 15, wherein the main regulator configured to supply power provided from an external battery.

19. The network element of claim 15, wherein the SoC is configured in a Wireless Personal Area Network (WPAN).

20. The network element of claim 15, wherein the clock unit, the main regulator, the processing circuitry, the PMU, and the one or more peripheral elements are all integrally formed in the SoC.