Systems and methods for CPU repair

• US 8,667,324 B2
• Filed: 02/17/2006
• Issued: 03/04/2014
• Est. Priority Date: 02/18/2005
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Barlow, Jeff, Brauch, Jeff, Calkin, Howard, Gratias, Raymond, Hack, Stephen, Joyal, Lacey, Kuntz, Guy, Pomaranski, Ken, Sedmak, Michael
• Primary Examiner(s): DUNCAN, MARC M
• Application Number:
  US11/356,521
• Publication Number:
  US 20060230230A1
• Time in Patent Office: 2,937 Days
• Field of Search: 714/7, 714/8, 714/42, 714/710, 714/711
• US Class Current: 714/6.13
• CPC Class Codes: G06F 12/121 using replacement algorithms

Abstract

In one embodiment, a cache element allocation method is provided. Each cache element on a CPU is assigned a quality rank based on the error rate of the cache element. If an allocated cache element is deemed to be faulty, the quality rank of the faulty allocated cache element is compared with the quality rank of the non-allocated cache elements. If a non-allocated cache element has a lower quality rank than the allocated cache element, the non-allocated cache element is swapped in for the allocated cache element.

Claims

1. A method for ranking CPU cache element quality, the method comprising:

logging cache error information following an error in a cache element; and

updating a cache error history database with said logged cache error information; and

evaluating said cache error history database to determine said quality rank, wherein said quality rank corresponds to a number of errors occurring in said cache element over a predetermined time period;

assigning said quality rank to said cache element.

2. The method of claim 1, wherein said cache error information includes which element said error occurred and when said error occurred.

3. The method of claim 1, further comprising storing said quality rank into a non-volatile memory.

4. A method for prolonging processor life, the method comprising:

logging cache error information following an error in a cache element;

updating a cache error history database with said logged cache error information;

evaluating said cache error history database to determine a quality rank of said cache element, wherein said quality rank corresponds to a total number of errors occurring in said cache element over a predetermined time period;

assigning said quality rank to said cache element;

determining that an allocated cache element is faulty based on said quality rank of said allocated cache element; and

swapping in a non-allocated cache element for said faulty allocated cache element.

5. The method of claim 4, further comprising determining whether said non-allocated cache element is available if said allocated cache element is determined to be faulty.

6. The method of claim 5, further comprising de-allocating said processor if said non-allocated cache element is not available.

7. The method of claim 6, further comprising swapping in a non-allocated processor for said de-allocated processor.

8. The method of claim 4, further comprising reporting actions taken and updating cache configuration on a memory device.

9. A CPU cache element management system comprising:

at least one processor having at least one allocated cache element and at least one non-allocated cache element;

a cache management logic operable to monitor cache errors and record cache error information in a memory and to log cache error information following an error in a cache element, to update a cache error history database with said logged cache error information, to evaluate said cache error history database to determine a quality rank, wherein said quality rank corresponds to a total number of errors occurring in said cache element over a predetermined period of time, and

wherein said cache management logic is further operable to swap in said non-allocated cache element for said allocated cache element if said allocated cache element is deemed faulty based on said quality rank.

10. The CPU cache element management system of claim 9, wherein said cache management logic is further operable to determine whether said non-allocated cache element is available if said allocated cache element is deemed faulty.

11. The CPU cache management system of claim 10, wherein said cache management logic is further operable to de-allocate said processor if said non-allocated cache element is not available.

12. The CPU cache management system of claim 11, wherein said cache management logic is further operable to swap in a non-allocated processor for said de-allocated processor.

13. The CPU cache management system of claim 9, wherein said cache management logic is further operable to report actions taken and update cache configuration on a memory device.

14. A computer system comprising:

at least one processor having at least one allocated cache element and at least one non-allocated cache element; and

a cache management logic operable to log cache error information following an error in a cache element, to update a cache error history database with said logged cache error information, to evaluate said cache error history database to determine a quality rank, wherein said quality rank corresponds to a total number of errors occurring in said cache element over a predetermined period of time, and

wherein said cache management logic is further operable to swap in said non-allocated cache element for said allocated cache element if said allocated cache element is deemed faulty based on said quality rank.

15. The computer system of claim 14, wherein said cache management logic is further operable to monitor cache errors and record cache error information in a memory.

16. The computer system of claim 14, wherein said cache management logic is further operable to determine whether said non-allocated cache element is available if said allocated cache element is deemed faulty.

17. The computer system of claim 16, wherein said cache management logic is further operable to de-allocate said processor if said non-allocated cache element is not available.

18. The computer system of claim 17, wherein said cache management logic is further operable to swap in a non-allocated processor for said de-allocated processor.

19. The computer system of claim 14, wherein said cache management logic is further operable to report actions taken and update cache configuration on a memory device.

20. A method for managing a computer system having an operating system comprising the steps of:

monitoring an allocated cache element on a processor for an error;

logging cache error information following said error in said allocated cache element;

updating a cache error history database with said logged cache error information;

evaluating said cache error history database to determine a quality rank for said allocated cache element;

assigning said quality rank to said allocated cache element corresponding to a total number of errors occurring in said allocated cache element over a predetermined time period; and

determining whether said allocated cache element is faulty based on said quality rank of said allocated cache element.

21. The method of claim 20, further comprising the steps of:

swapping in a non-allocated cache element if said non-allocated cache element is available and said allocated cache element is faulty while said operating system is running; and

updating cache configuration in a memory.