Semiconductor integrated circuit device, method of controlling the semiconductor integrated circuit device and information processing system

• US 8,667,346 B2
• Filed: 01/24/2013
• Issued: 03/04/2014
• Est. Priority Date: 07/29/2010
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Iwami, Yoshikazu, Sakamaki, Hideyuki
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US13/749,079
• Publication Number:
  US 20130139016A1
• Time in Patent Office: 404 Days
• Field of Search: 714/718, 714/731, 714/724, 714/726, 714/733, 714/734
• US Class Current: 714/718
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals
• CPC Class Codes: G01R 31/318555 Control logic

Abstract

A debug system scans a scan memory element group having a plurality of scan memory elements which are connected in series in a semiconductor integrated circuit device and collects data in the scan memory element group. The semiconductor integrated circuit device has an end code register which is provided between an input terminal and an input side of the scan memory element group and holds an end code, a start code register which is provided between an output terminal and an output side of the scan memory element group and holds a start code, and a scan control circuit which controls shift operations of the scan memory element group, the end code register and the start code register, and outputs scan data to the output terminal.

Claims

1. A semiconductor integrated circuit device comprising:

a scan memory element group that a plurality of scan memory elements are connected in series;

an end code register that is provided between an input terminal and an input side of the scan memory element group and holds an end code;

a start code register that is provided between an output terminal and an output side of the scan memory element group and holds a start code; and

a scan control circuit that controls shift operations of the scan memory element group, the end code register and the start code register and outputs scan data to the output terminal.

2. The semiconductor integrated circuit device according to claim 1, wherein the scan control circuit writes the start code which is inputted into the start code register and writes the end code which is inputted into the end code register.

3. The semiconductor integrated circuit device according to claim 1,

wherein the scan memory element group comprises a plurality of blocks, each of which the plurality of scan memory elements are connected in series, and

wherein the scan control circuit controls that the plurality of blocks are connected in series in response to an instruction of a single chain, and controls that a designated block among the plurality of blocks is connected to the end code register and the start code register in accordance with an instruction of an individual chain.

4. The semiconductor integrated circuit device according to claim 3,

wherein the device further comprises a bypass register that holds bypass data to designate the block to be bypassed, and

wherein the scan control circuit forms a single chain that connects the plurality of blocks except the block that is specified by the bypass register, in series.

5. The semiconductor integrated circuit device according to claim 4, wherein the scan control circuit writes the bypass data which is inputted into the bypass register.

6. The semiconductor integrated circuit device according to claim 1,

wherein the device further comprises a functional circuit that performs a predetermined function, and

wherein the scan memory element group hold status of the functional circuit.

7. The semiconductor integrated circuit device according to claim 3, wherein the scan control circuit comprises:

a chain control circuit that controls that the plurality of blocks are connected in series in response to the instruction of the single chain, and controls that the designated block among the plurality of blocks is connected to the end code register and the start code register in accordance with the instruction of the individual chain; and

a data scan selection circuit that analyzes an instruction code from the input terminal, provides the instruction of chain and provides a shift clock to the scan memory element group, the end code register and the start code register.

8. The semiconductor integrated circuit device according to claim 7,

wherein the device further comprises a bypass register that holds bypass data to designate the block to be bypassed, and

wherein the scan control circuit forms a single chain that connects the plurality of blocks except the block that is specified by the bypass register, in series.

9. A method of controlling of a semiconductor integrated circuit device, the method comprising:

connecting an end code register, which holds an end code, to an input side of a scan memory element group in which a plurality of scan memory elements are connected in series;

connecting a start code register, which holds a start code, to an output side of the scan memory element group;

controlling a shift operation of the scan memory element group, the end code register, and the start code register; and

outputting scan data to the output terminal to collect data of the scan memory element group.

10. The method of controlling a semiconductor integrated circuit device according to claim 9, the method further comprises:

writing the start code from the input terminal into the start code register; and

writing the end code from the input terminal into the end code register.

11. The method of controlling a semiconductor integrated circuit device according to claim 9, the method further comprises:

connecting a plurality of blocks, each comprising a plurality of scan memory elements which are connected in series in the scan memory element group, in response to an instruction of a single chain; and

connecting a designated block among the plurality of blocks to the end code register and the start code register in accordance with an instruction of an individual chain.

12. The method of a semiconductor integrated circuit device according to claim 11, wherein the method further comprises forming a single chain that connects the plurality of blocks except the block that is specified by a bypass register that holds bypass data to specify the block to be bypassed, in series.

13. The method of a semiconductor integrated circuit device according to claim 11, wherein the method further comprises writing the bypass data from the input terminal into the bypass register.

14. The method of a semiconductor integrated circuit device according to claim 11, wherein the scan memory element group hold status of the functional circuit that performs a predetermined function.

15. The method of a semiconductor integrated circuit device according to claim 12, wherein the method further comprises:

analyzing an instruction code from the input terminal and providing the instruction of chain;

providing a shift clock to the scan memory element group, the end code register and the start code register;

connecting the plurality of blocks in series in response to the instruction of the single chain; and

connecting the designated block among the plurality of blocks to the end code register and the start code register in accordance with the instruction of the individual chain.

16. An information processing system comprising:

a processing device having a semiconductor integrated circuit that performs information processing; and

a system control device that monitors the processing device,

wherein the semiconductor integrated circuit comprises;

a functional circuit that performs the information processing;

a scan memory element group that a plurality of scan memory elements are connected in series;

an end code register that is provided between an input terminal connected to the system control device and an input side of the scan memory element group and holds an end code;

a start code register that is provided between an output terminal connected to the system control device and an output side of the scan memory element group and holds a start code; and

a scan control circuit that controls shift operations of the scan memory element group, the end code register and the start code register and outputs scan data to the output terminal.

17. The information processing system according to claim 16, wherein the scan control circuit writes the start code which is inputted into the start code register and writes the end code which is inputted into the end code register.

18. The information processing system according to claim 16, wherein the scan memory element group comprises a plurality of blocks, each of which the plurality of scan memory elements are connected in series, and

wherein the scan control circuit controls that the plurality of blocks are connected in series in response to an instruction of a single chain, and controls that a designated block among the plurality of blocks is connected to the end code register and the start code register in accordance with an instruction of an individual chain.

19. The information processing system according to claim 18, wherein the semiconductor integrated circuit device further comprises a bypass register that holds bypass data to designate the block to be bypassed, and

wherein the scan control circuit forms a single chain that connects the plurality of blocks except the block that is specified by the bypass register, in series.

20. The information processing system according to claim 19, wherein the scan control circuit writes the bypass data which is inputted into the bypass register.