Method of etching self-aligned vias and trenches in a multi-layer film stack

• US 8,668,835 B1
• Filed: 01/23/2013
• Issued: 03/11/2014
• Est. Priority Date: 01/23/2013
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Indrakanti, Ananth, Nagabhirava, Bhaskar
• Primary Examiner(s): Culbert, Robert
• Application Number:
  US13/748,249
• Time in Patent Office: 412 Days
• Field of Search: 216/17, 438/689, 438/694, 438/700
• US Class Current: 216/17
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/67069 for drying etching
• CPC Class Codes: H01L 21/67109 mainly by convection
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch
• CPC Class Codes: H01L 21/76832 Multiple layers

Abstract

A multi-step etch process wherein elliptical via openings and trench openings are formed in a dielectric layer includes supporting a multi-layer film stack on a temperature controlled electrostatic chuck in a plasma etch reactor. The multi-layer film stack has a dielectric layer and a patterned metal hard mask layer above the dielectric layer. An etchant gas is supplied to the plasma etch reactor. The etchant gas is energized into a plasma state, and via openings in a photo resist are transferred into a planarization layer and then into elliptical portions of the trench openings in a patterned hard mask layer while maintaining the chuck at a temperature of about 30 to 50° C. The elliptical openings are extended into a lower layer of the hard mask and into an underlying dielectric layer while maintaining the chuck at a temperature of 20° C. or below. After stripping the planarization layer to expose the trench pattern in the hard mask, trench openings are formed in the dielectric layer while maintaining the chuck at a temperature of about 55° C. or higher. The process can thus provide enlarged via contact areas while etching trenches with pitches of 80 nm or less.

Claims

1. A method of etching self-aligned vias and trenches in a multi-layer film stack supported by a temperature controlled electrostatic chuck in a plasma processing apparatus wherein the temperature controlled electrostatic chuck adjusts the temperature of the multi-layer film stack during etching of the self-aligned vias and trenches, the method comprising:

etching via openings into a planarization layer beneath a previously patterned photo resist mask while maintaining the multi-layer film stack at a temperature of about 30 to 50°

C., the planarization layer overlying and filling trench openings in a metal hard mask previously patterned to form trenches, the via openings in the planarization layer being larger than the trench openings, the etching being carried out until planarization material in the trench openings is removed and elliptical via openings are formed in areas of the trench openings where the planarization material is removed;

etching elliptical via openings into a hard mask layer beneath the metal hard mask while maintaining the multi-layer film stack at a temperature of about 0 to 20°

C.;

etching elliptical via openings into a dielectric layer beneath the hard mask layer by transferring the pattern of elliptical via openings in the hard mask layer into the dielectric layer and continuing the etching until the elliptical via openings reach an etch stop layer beneath the dielectric layer while the multi-layer stack is maintained at a temperature below about 50°

C.;

stripping the planarization layer to expose the pattern of trench openings in the metal hard mask;

etching trenches into the dielectric layer by transferring the pattern of trench openings in the hard mask layer into the dielectric layer, while etching the elliptical via openings through the etch stop layer, wherein the trench etch is performed while the multi-layer stack is maintained at a temperature of above about 55°

C.

2. The method of claim 1, further comprising etching the elliptical via openings into a dielectric barrier layer beneath the etch stop layer while the multi-layer stack is maintained at a temperature of above about 55°

C.

3. The method of claim 1, wherein the photo resist mask is above a silicon containing anti-reflective coating (SiARC), and the planarization layer is an organic planarization layer (OPL).

4. The method of claim 1, wherein the elliptical via openings have vertical sidewalls.

5. The method of claim 1, wherein the metal hard mask is formed from a material selected from the group consisting of TiN, SiN, WN, WSiN, TiSiN, TaN, TaSiN, TiTaN, TaRuN, and combinations thereof.

6. The method of claim 1, wherein the metal hard mask layer is formed from TiN.

7. A method of etching self-aligned vias and trenches in a multi-layer film stack wherein patterns of openings in layers of the multi-layer film stack are transferred into one or more underlying layers of the multi-layer film stack by performing a multi-step plasma etching process in a plasma etching apparatus wherein a semiconductor substrate is supported on a temperature controlled chuck;

the method comprising;

transferring a pattern of via openings having a critical dimension (CD1) in a patterned mask layer into an underlying planarization layer, wherein the planarization layer overlies and fills a pattern of trench openings having a critical dimension (CD2) in a patterned hard mask layer, CD1 is larger than CD2 and at least some of the via openings in the patterned mask layer are vertically aligned with the trench openings in the hard mask layer;

transferring the via openings in the planarization layer into the filled trench openings in the hard mask layer so as to form elliptical via openings, the elliptical via openings having critical dimensions CD1 in a direction along a length of the trenches and critical dimensions CD2 in a transverse direction across a width of the trenches;

transferring the elliptical via openings into an underlying dielectric layer;

stripping the planarization layer such that the patterned hard mask layer is exposed;

transferring the pattern of trench openings in the hard mask layer into the underlying dielectric layer such that at least some of the trenches are formed over the elliptical via openings and the elliptical via openings are extended further into the dielectric layer, the trench openings and elliptical via openings having substantially the same critical dimension CD1 in the transverse direction.

8. The method of claim 7, wherein the patterned mask layer includes a silicon containing antireflection layer (SiARC) beneath a photoresist patterned with circular via openings and the hard mask layer includes a metal hard mask layer between upper and lower silicon containing hard mask layers, the method including transferring the via openings into the SiARC prior to transferring the via openings into the planarization layer and transferring the elliptical via openings into the lower silicon containing hard mask layer prior to transferring the elliptical via openings into the dielectric layer.

9. The method of claim 7, wherein the patterned hard mask layer includes a lower hard mask (HM1) layer, a metal hard mask (MHM) layer over the HM1 layer, and an upper hard mask (HM2) layer over the MHM layer, the MHM layer and the HM2 layer including the patterned trench openings, the method including transferring the elliptical via openings into the HM1 layer.

10. The method of claim 9, wherein transferring the pattern of via openings in the planarization layer into the patterned hard mask layer exposes a portion of the upper surface of the MHM layer.

11. The method of claim 9, wherein the MHM layer is formed from a material selected from the group consisting of TiN, SiN, WN, WSiN, TiSiN, TaN, TaSiN, TiTaN, TaRuN and combinations thereof and the HM1 And HM2 layers are formed from a material selected from the group consisting of silicon carbide, silicon nitride, silicon oxide, SiON, TEOS and combinations thereof.

12. The method of claim 7, wherein the multilayer stack includes an etch stop layer beneath the dielectric layer and a barrier layer below the etch stop layer, the method including transferring the elliptical via openings into the etch stop layer before stripping the planarization layer, extending the elliptical via openings through the etch stop layer during the step of transferring the trench openings into the dielectric layer, and subsequently transferring the elliptical via openings into the barrier layer.

13. The method of claim 7, wherein the pattern of via openings in the patterned mask layer is transferred to the underlying planarization layer while maintaining the chuck at a temperature of about 30 to 50°

C., the elliptical via openings are transferred into the dielectric layer while maintaining the chuck at a temperature below about 20°

C., and the trench openings are transferred into the dielectric layer while maintaining the chuck at a temperature above about 55°

C.

14. The method of claim 8, wherein the elliptical via openings are transferred into the lower silicon containing hard mask layer while maintaining the chuck below about 20°

C.

15. The method of claim 7, wherein the trench openings have a pitch of 80 nm or less and the elliptical via openings have CD2 at least about 1.5 times larger than CD1.

16. The method of claim 7, wherein the patterned hard mask layer includes a TiN layer and portions of the TiN layer are exposed to plasma during etching of the pattern of trench openings in the hard mask layer into the underlying dielectric layer while maintaining the chuck at a temperature of about 50 to 70°

C.

17. The method of claim 7, wherein the plasma etch reactor comprises a dual-frequency medium-density capacitively coupled plasma reactor including an upper showerhead electrode and a bottom electrode, RF energy being supplied at two different frequencies to either the bottom electrode or at different first and second frequencies to the showerhead electrode and bottom electrode.

18. The method of claim 17, wherein RF energy is supplied at two different frequencies to the bottom electrode or at different first and second frequencies to the showerhead electrode and bottom electrode wherein the frequencies of RF energy are selected from the group consisting of 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, and 90 MHz.

19. The method of claim 7, wherein bottoms of the elliptical via openings contact conductive lines with contact areas having widths of about CD1 and lengths of about CD2.

20. The method of claim 7, wherein the trench openings are vertically aligned with at least two of the elliptical via openings.