Through-wafer interconnects for photoimager and memory wafers

• US 8,669,179 B2
• Filed: 07/11/2013
• Issued: 03/11/2014
• Est. Priority Date: 09/02/2004
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman, Watkins, Charles M., Hiatt, William M., Hembree, David R., Wark, James M., Farnworth, Warren M., Tuttle, Mark E., Rigg, Sidney B., Oliver, Steven D., Kirby, Kyle K., Wood, Alan G., Velicky, Lu
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US13/940,034
• Publication Number:
  US 20130295766A1
• Time in Patent Office: 243 Days
• Field of Search: 438/667
• US Class Current: 438/667
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 27/14634 : Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 : Interconnect structures
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Claims

1. A method of forming a microelectronic assembly, the method comprising:

exposing at least a portion of a first surface of a bond-site covered by a passivation layer, wherein the bond-site has a second surface opposite the first surface that faces a front side of a substrate;

disposing a first conductive layer on at least a portion of the first surface of the bond-site;

exposing at least a portion of the front side of the substrate through the bond-site;

forming a via in the substrate extending to an intermediate depth from the front side of the substrate;

disposing a dielectric on a sidewall of the via and on the first conductive layer;

removing the dielectric from an uppermost surface of the assembly;

applying a second conductive material on the dielectric;

filling the via with a third conductive material; and

exposing the third conductive material from a back side of the substrate.

2. The method of claim 1 wherein:

prior to exposing at least a portion of the front side of the wafer the method comprises forming an opening extending through the bond-site; and

disposing the first conductive layer on at least a portion of the first surface of the bond-site comprises disposing the first conductive layer on the first surface generally surrounding the opening extending through the bond-site.

3. The method of claim 2 wherein forming an opening extending through the bond-site comprises exposing at least a portion of an insulation layer positioned between the bond-site and the front side of the substrate.

4. The method of claim 1 wherein disposing the dielectric on the sidewall of the via and the first conductive layer further comprises disposing the dielectric on at least a portion of the bond-site.

5. The method of claim 1 wherein applying the second conductive material further comprises applying the second conductive material on an uppermost surface of the assembly.

6. The method of claim 5, further comprising disposing a protective layer on the second conductive material and generally surrounding the via.

7. The method of claim 1 wherein filling the via with the third conductive material comprises filling the via with the third conductive material such that the third conductive material projects from an uppermost surface of the assembly.

8. The method of claim 1 wherein exposing the third conductive material from the backside of the substrate comprising removing a portion of the substrate such that the third conductive material protrudes from the backside of the substrate.

9. The method of claim 8 wherein the passivation layer is a first passivation layer, and wherein the method further comprises

applying a second passivation layer on the backside of the substrate and the third conductive material;

and

exposing the third conductive material through the second passivation layer.

10. A method of forming a microelectronic assembly, the method comprising:

exposing at least a portion of a bond pad carried by a first side of a substrate;

applying a first conductor to an exposed surface of the bond pad;

exposing the first side of the substrate through the bond pad;

forming an opening extending into the substrate from the first side;

disposing a dielectric layer on a sidewall of the opening;

applying a second conductor on the dielectric layer within the opening;

filling the opening with a third conductive material; and

exposing the third conductive material from a second side of the substrate, wherein the second side of the substrate is opposite the first side.

11. The method of claim 10 wherein forming an opening extending into the substrate from the first side comprises forming a blind hole extending to an intermediate depth within the substrate.

12. The method of claim 10 wherein disposing a dielectric layer on a sidewall of the opening comprises disposing the dielectric layer such that it directly contacts at least a portion of the bond pad.

13. The method of claim 10 wherein applying a second conductor on the dielectric layer within the opening comprises applying the second conductor such that it comprises at least a portion of an uppermost surface of the assembly.