Thin film transistors

• US 8,669,553 B2
• Filed: 07/02/2010
• Issued: 03/11/2014
• Est. Priority Date: 07/02/2010
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.), Oregon State University (Oregon University System)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.), Oregon State University (Oregon University System)
• Inventors: Knutson, Chris, Presley, Rick, Wager, John F., Keszler, Douglas, Hoffman, Randy
• Primary Examiner(s): Lebentritt, Michael
• Assistant Examiner(s): Quinto, Kevin
• Application Number:
  US13/704,012
• Publication Number:
  US 20130092931A1
• Time in Patent Office: 1,348 Days
• Field of Search: None
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin-film transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, a channel layer, and a passivation layer. The channel layer has a first surface and an opposed second surface, where the first surface is disposed over at least a portion of the gate dielectric. The channel layer also has a first oxide composition including at least one predetermined cation. The passivation layer is disposed adjacent to at least a portion of the opposed second surface of the channel layer. The passivation layer has a second oxide composition including the at least one predetermined cation of the first oxide composition and at least one additional cation that increases a bandgap of the passivation layer relative to the channel layer.

Claims

1. A thin-film transistor, comprising:

a gate electrode;

a gate dielectric disposed on the gate electrode;

a channel layer having a first surface and an opposed second surface, the first surface being disposed over at least a portion of the gate dielectric, the channel layer having a first oxide composition including at least one predetermined cation; and

a passivation layer disposed adjacent to at least a portion of the opposed second surface of the channel layer, the passivation layer including a second oxide composition including the at least one predetermined cation of the first oxide composition and at least one additional cation that increases a bandgap of the passivation layer relative to the channel layer.

2. The thin-film transistor as defined in claim 1 wherein the at least one predetermined cation of the first oxide composition is selected from:

indium, gallium, tin, zinc, and combinations thereof; and

wherein the at least one additional cation of the second oxide composition is selected from of;

aluminum, boron, hafnium, magnesium, niobium, silicon, tantalum, yttrium, zirconium, and combinations thereof.

3. The thin-film transistor as defined in claim 2 wherein the first oxide composition is zinc tin oxide and the second oxide composition is selected from zinc tin aluminum oxide and zinc tin silicon oxide, or wherein the first oxide composition is zinc indium oxide and the second oxide composition is selected from zinc indium aluminum oxide and zinc indium silicon oxide.

4. The thin-film transistor as defined in claim 1 wherein an amount of the at least one additional cation element in the second oxide composition ranges from about 20 atomic % to about 70 atomic % of total cation species in the second oxide composition.

5. The thin-film transistor as defined in claim 1, further comprising a second passivation layer disposed adjacent to the passivation layer, the second passivation layer being selected from aluminum oxide, hafnium oxide silicon nitride, silicon oxide, silicon oxynitride, and zirconium oxide.

6. The thin-film transistor as defined in claim 1, further comprising:

at least one drain electrode in electrical contact with the channel layer; and

at least one source electrode in electrical contact with the channel layer;

wherein the passivation layer is positioned on the opposed second surface of the channel layer and covers at least an area between the at least one source electrode and the at least one drain electrode.

7. The thin-film transistor as defined in claim 1, wherein the first oxide composition includes at least one dopant species selected from aluminum, hydrogen, and nitrogen, and wherein the at least one dopant species is present in an amount ranging from 0.5 atomic % to 4 atomic % of all species present in the first oxide composition.

8. A thin-film transistor, comprising:

a substrate;

a gate electrode disposed on the substrate;

a gate dielectric disposed on the gate electrode;

a channel layer having a first surface and an opposed second surface, the first surface being disposed over at least a portion of the gate dielectric, the channel layer having a first oxide composition including at least one cation selected from zinc, tin, indium, and gallium;

at least one drain electrode in electrical contact with the channel layer;

at least one source electrode in electrical contact with the channel layer;

a passivation layer disposed adjacent to at least a portion of the second opposed surface of the channel layer, the passivation layer having a second oxide composition including the at least one cation of the first oxide composition and at least one additional cation selected from aluminum, boron, hafnium, magnesium, niobium, silicon, tantalum, yttrium, and zirconium; and

a second passivation layer disposed adjacent to the passivation layer, the second passivation layer being selected from aluminum oxide, hafnium oxide, silicon nitride, silicon oxide, silicon oxynitride, and zirconium oxide.

16. The thin-film transistor as defined in claim 8 wherein the first oxide composition is zinc tin oxide and the second oxide composition is selected from zinc tin aluminum oxide and zinc tin silicon oxide, or wherein the first oxide composition is zinc indium oxide and the second oxide composition is selected from zinc indium aluminum oxide and zinc indium silicon oxide.

17. The thin-film transistor as defined in claim 8 wherein an amount of the at least one additional cation element in the second oxide composition ranges from about 20 atomic % to about 70 atomic % of total cation species in the second oxide composition.

9. A method of forming a structure, comprising:

selecting a first oxide composition including at least one predetermined cation, and second oxide composition including the at least one predetermined cation of the first oxide composition and at least one additional cation that increases a bandgap of the second oxide composition relative to the first oxide composition;

depositing the first oxide composition over at least a portion of a gate dielectric to form a channel layer; and

passivating an exposed portion of the channel layer with the second oxide composition to form a passivation layer.

10. The method as defined in claim 9 wherein the selecting of the first oxide composition includes selecting an oxide of:

indium, gallium, tin, zinc, and combinations thereof; and

wherein the selecting of the second oxide composition includes selecting the additional cation from the group consisting of aluminum, boron, hafnium, magnesium, niobium, silicon, tantalum, yttrium, zirconium, and combinations thereof.

11. The method as defined in claim 9 wherein passivating the exposed portion of the channel layer is accomplished using a vacuum deposition technique and a photolithographic patterning technique.

12. The method as defined in claim 11 wherein after forming the passivation layer, the method further comprises annealing the structure in air at a predetermined temperature ranging from about 150°

C. to about 400°

C. for a predetermined time ranging from about 5 minutes to about 2 hours.

13. The method as defined in claim 9 wherein prior to passivating the exposed portion of the channel layer, the method further comprises:

depositing at least one drain electrode in electrical contact with a portion of the channel layer; and

depositing at least one source electrode in electrical contact with an other portion of the channel layer;

wherein the depositing of each of the at least one drain electrode and the at least one source electrode defines the exposed portion of the channel layer.

14. The method as defined in claim 9, further comprising depositing a second passivation layer adjacent to the passivation layer, the second passivation layer being selected from aluminum oxide, hafnium oxide, silicon nitride, silicon oxide, silicon oxynitride, and zirconium oxide.

15. The method as defined in claim 9 wherein prior to passivating the exposed portion of the channel layer, the method further comprises annealing the structure in air at a predetermined temperature ranging from about 150°

C. to about 400°

C. for a predetermined time ranging from about 5 minutes to about 2 hours.