Methods and apparatus for non-volatile memory cells with increased programming efficiency

• US 8,669,607 B1
• Filed: 11/01/2012
• Issued: 03/11/2014
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsair, Yong-Shiuan, Chu, Wen-Ting, Liu, Po-Wei, Huang, Wen-Tuo, Yang, Yu-Hsiang, Chiu, Chieh-Fei, Hsu, Yu-Ling
• Primary Examiner(s): Dang, Trung Q
• Application Number:
  US13/666,712
• Time in Patent Office: 495 Days
• Field of Search: 257/316, 257/E29.129, 257/E29.3, 438/257
• US Class Current: 257/316
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Claims

1. An apparatus, comprising:

a semiconductor substrate having a source region formed in the semiconductor substrate and having a drain region formed in the semiconductor substrate, spaced from the source region;

a floating gate region formed over the semiconductor substrate and disposed between the source region and the drain region, the floating gate having a source side sidewall and an upper surface;

a control gate formed over a portion of the floating gate, the control gate having a source side sidewall adjacent the source region in the semiconductor substrate and a drain side sidewall adjacent the drain region, a portion of the upper surface of the floating gate adjacent the source region and the drain region not covered by the control gate, the source side sidewall of the control gate having a source side sidewall spacer of a first thickness and the drain side sidewall of the control gate having a drain side sidewall spacer of a second thickness greater than the first thickness, the drain side sidewall spacer comprising an L-shaped liner over the floating gate, the source sidewall spacer having no L-shaped liners, the source side sidewall spacer and the drain side sidewall spacer of the control gate being asymmetric with respect to one another;

an inter-poly dielectric over the source side sidewalls and the upper surface of the floating gate adjacent the source region; and

an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region.

2. The apparatus of claim 1, wherein the erase gate overlying at least a portion of the upper surface of the floating gate covers at least 5 percent of the upper surface of the floating gate.

3. The apparatus of claim 1, wherein the erase gate overlying at least a portion of the upper surface of the floating gate covers between 5 and 20 percent of the upper surface of the floating gate.

4. The apparatus of claim 1, wherein the erase gate overlying at least a portion of the upper surface of the floating gate covers between 5 and 10 percent of the upper surface of the floating gate.

5. The apparatus of claim 1 and further comprising a select gate formed overlying the drain region of the semiconductor substrate adjacent the drain side sidewall of the control gate.

6. The apparatus of claim 1, wherein at least one of the source side sidewall spacer and the drain side sidewall spacer of the control gate is formed of composite spacers comprising a nitride spacer adjacent the control gate and of an oxide spacer overlying the nitride spacer.

7. The apparatus of claim 6, wherein the L-shaped liner is the nitride spacer and the oxide spacer is over the L-shaped liner.

8. The apparatus of claim 6, wherein the drain side sidewall spacer of the control gate has a portion that extends horizontally from the control gate that covers a portion of the upper surface of the floating gate.

9. An apparatus comprising:

a common source region formed in a semiconductor substrate;

at least a first drain region and a second drain region formed in the semiconductor substrate on opposite sides of and each spaced from the common source region;

at least a first and a second floating gate formed over the semiconductor substrate adjacent to opposite sides of the common source region and disposed between the common source region and the first and second drain regions;

a first control gate formed over a portion of the first floating gate, and a second control gate formed over a portion of the second floating gate, each of the first and second floating gates having a portion of the upper surface that is not covered by the respective first and second control gates along a respective drain side and a respective source side;

each of the first and second control gates having a drain side sidewall spacer, each drain side sidewall spacer formed of a composite spacer that extends vertically along the vertical side of the respective first and second control gates, each drain side sidewall spacer comprising an L-shaped liner over the floating gate and having an outer edge aligned with a lateral edge of the floating gate, the source side sidewall spacer no L-shaped liners over the floating gate and having an outer edge aligned with a lateral edge of the floating gate;

each of the first and second control gates having a source side sidewall spacer, each of the source side sidewall spacers formed of the composite spacer that extends vertically along a vertical side of the respective one of the first and second control gates adjacent the common source region, wherein the drain side sidewall spacers have a first thickness and the source side sidewall spacers have a second thickness less than the first thickness; and

an erase gate formed over the common source region in the semiconductor substrate overlying a portion of the upper surface each of the first and second floating gates.

10. The apparatus of claim 9, wherein the erase gate overlying at least a portion of the upper surface of the first and second floating gates covers between 5 and 20 percent of the upper surface of the respective first and second floating gate.

11. The apparatus of claim 9, wherein the source side sidewall spacers and the drain side sidewall spacers of the first and second control gates are each formed of composite spacers comprising a nitride spacer adjacent the respective first and second control gate and of an oxide spacer overlying the nitride spacer.

12. The apparatus of claim 9 wherein the drain side sidewall spacers of the first and second control gates each have an L shape at the bottom portion, adjacent to and extending horizontally over the upper surface of the respective one of the first and second floating gates.

13. The apparatus of claim 9 wherein the source side sidewall spacers of the first and second control gates ends at the upper surface of the respective one of the first and second floating gates and does not extend horizontally substantially over the upper surface of the floating gate.

14. The apparatus of claim 9 wherein the source side sidewall spacer of the respective first and second control gate is covered with an interpoly dialectic.

15. A method, comprising:

forming a floating gate layer over a semiconductor substrate, the floating gate layer having an upper surface, forming a control gate layer over a portion of the upper surface of the floating gate layer, and patterning the control gate layer to form a control gate having a source side sidewall adjacent a common source region in the semiconductor substrate, and a drain side sidewall adjacent a drain region in the semiconductor substrate;

depositing a composite spacer over the control gate and the floating gate layer;

removing the composite spacer from the upper surface of the floating gate layer not covered by the control gate and patterning the composite spacer over the control gate, forming asymmetric sidewall spacers on the control gate, a source side sidewall spacer being thicker than a drain side sidewall spacer;

using the source side sidewall and drain side sidewall spacers as a mask, etching the floating gate layer to form a floating gate partially covered by the control gate;

removing the oxide from the source side sidewall of the control gate and from a portion of the floating gate adjacent the common source region, so that a portion of the floating gate adjacent the common source region has an exposed upper surface; and

forming an erase gate over the common source region in the substrate and overlying the floating gate, the erase gate being adjacent to the source side sidewall of the control gate and overlying at least a portion of the upper surface of the floating gate.

16. The method of claim 15, wherein the erase gate overlies at least 5 percent of the upper surface of the floating gate.

17. The method of claim 15, wherein the erase gate overlies between 5 and 20 percent of the upper surface of the floating gate.

18. The method of claim 15, wherein the erase gate overlies between 5 and 10 percent of the upper surface of the floating gate.

19. The method of claim 15, and further comprising performing an ion implant in the common source region to form a doped source in the semiconductor substrate.