Structure related to a thick bottom dielectric (TBD) for trench-gate devices

• US 8,669,623 B2
• Filed: 08/27/2010
• Issued: 03/11/2014
• Est. Priority Date: 06/20/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Pan, James, Rexer, Christopher Lawrence
• Primary Examiner(s): Nhu, David
• Application Number:
  US12/870,600
• Publication Number:
  US 20100320534A1
• Time in Patent Office: 1,292 Days
• Field of Search: 257/396, 257/288, 257/281, 257/284, 257/192, 257/330, 257/401, 257/E21.027, 257/E21.051, 257/E21.058, 257/E21.17, 257/E21.267, 257/E21.221, 257/E21.351, 257/E21.364, 257/E21.214, 257/E21.545, 257/E21.546, 257/E21.229, 257/E21.278, 257/E21.293
• US Class Current: 257/396
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor structure which includes a shielded gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A shield dielectric is formed extending along at least lower sidewalls of each trench. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. A shield electrode is formed in a bottom portion of each trench. A gate electrode is formed over the shield electrode in each trench.

Claims

1. A semiconductor structure, comprising:

a trench disposed in a semiconductor region and including a sidewall, a lower portion, and a bottom portion;

a shield electrode disposed in the lower portion of the trench;

a gate electrode disposed in an upper portion of the trench;

a sidewall dielectric lining a sidewall of the trench;

a thick bottom dielectric lining the bottom portion of the trench, a thickness of the thick bottom dielectric being different than a thickness of the sidewall dielectric; and

a mesa surface disposed adjacent to the trench, the thick bottom dielectric not being disposed over any portion of the mesa surface.

2. The semiconductor structure of claim 1, the thickness of the thick bottom dielectric being greater than the thickness of the sidewall dielectric.

3. The semiconductor structure of claim 1, further comprising:

a drift region, and

the trench being disposed in the drift region.

4. The semiconductor structure of claim 1, further comprising:

a Schottky diode formed in a non-FET region.

5. The semiconductor structure of claim 1, further comprising:

a dielectric dome disposed over the trench, and

the gate electrode disposed between the thick bottom dielectric, the sidewall dielectric, and the dielectric dome.

6. The semiconductor structure of claim 1, further comprising:

a gate dielectric lining the upper portion of the trench.

7. The semiconductor structure of claim 6, wherein the gate dielectric has a thickness less than the thickness of the sidewall dielectric.

8. The semiconductor structure of claim 1, further comprising an inter-electrode dielectric disposed between the shield electrode and the gate electrode.

9. The semiconductor structure of claim 1, wherein the shield electrode includes undoped polysilicon.

10. The semiconductor structure of claim 1, further comprising:

a drift region including a top surface, and

the shield electrode including a top surface that is disposed below the top surface of the drift region.

11. The semiconductor structure of claim 1, wherein the thickness of the thick bottom dielectric is greater than the thickness of the sidewall dielectric.

12. An apparatus, comprising:

a field-effect transistor (FET) region including;

a FET trench disposed in a semiconductor region and including a sidewall and a bottom portion,

a FET sidewall dielectric lining a sidewall of the FET trench,

a FET shield electrode disposed in a lower portion of the FET trench,

a FET gate electrode disposed in an upper portion of the FET trench, and

a FET thick bottom dielectric lining the bottom portion of the FET trench, the FET thick bottom dielectric having a thickness different than a thickness of the FET sidewall dielectric; and

a non-field-effect transistor (FET) region including;

a non-FET trench disposed in the semiconductor region and including a sidewall and a bottom portion,

a non-FET sidewall dielectric lining a sidewall of the non-FET trench, and

a non-FET thick bottom dielectric lining the bottom portion of the non-FET trench, the non-FET thick bottom dielectric having a thickness different than a thickness of the non-FET sidewall dielectric.

13. The apparatus of claim 12, wherein the non-FET region includes a Schottky diode,

the Schottky diode includes the non-FET trench, the non-FET sidewall dielectric, and the non-FET thick bottom dielectric.

14. The apparatus of claim 12, further comprising:

an interconnect layer functioning as an anode electrode of the non-FET region and as a source interconnect of a source region of the FET region.

15. The apparatus of claim 12, wherein the non-FET region is a first non-FET trench,

the apparatus further comprising:

a second non-FET trench, and

a mesa surface disposed between the first non-FET trench and the second non-FET trench; and

an interconnect layer disposed over the FET region and over the non-FET region such that the interconnect layer contacts the mesa surface and contacts a source region of the FET region.

16. The apparatus of claim 12, further comprising:

an interconnect layer disposed over the FET region and over the non-FET region such that the interconnect layer contacts a mesa surface included in the non-FET region to form a Schottky contact.

17. The apparatus of claim 12, wherein the FET region further including:

a FET inter-electrode dielectric disposed between the FET shield electrode and the FET gate electrode;

a FET shield dielectric lining the lower portion of the sidewall of the FET trench; and

a FET gate dielectric lining the upper portion of the sidewall of the FET trench, the FET gate dielectric having a thickness less than a thickness of the FET shield dielectric.

18. An apparatus, comprising:

a field-effect transistor (FET) region including;

a first trench disposed in a semiconductor region and including a sidewall and a bottom portion,

a sidewall dielectric lining a sidewall of the trench,

a shield electrode disposed in a lower portion of the trench,

a gate electrode disposed in an upper portion of the trench, and

a first thick bottom dielectric lining the bottom portion of the trench, the thick bottom dielectric having a thickness greater than a thickness of the sidewall dielectric; and

a Schottky diode disposed in a non-field-effect transistor (FET) region, the Schottky diode including a conductive layer contacting a mesa surface to form a Schottky contact,

the non-FET region including;

a second trench; and

a second thick bottom dielectric lining the bottom portion of the second trench, the second thick bottom dielectric having a thickness equal to the thickness of the first thick bottom dielectric.

19. The apparatus of claim 18, wherein the shield electrode is a first shield electrode,

the FET region further including:

an inter-electrode dielectric disposed between the first shield electrode and the gate electrode; and

a second shield electrode disposed in the second trench.

20. The apparatus of claim 18, wherein the gate electrode is a first gate electrode and the shield electrode is a first shield electrode,

the FET region further including:

a second gate electrode disposed in the second trench; and

a second shield electrode disposed in the second trench.

21. The apparatus of claim 18, wherein the non-FET region further including:

a mesa surface disposed adjacent to the second trench, the second thick bottom dielectric not being disposed over any portion of the mesa surface.

22. The apparatus of claim 18, wherein the FET region further including:

a mesa surface disposed adjacent to the first trench, the first thick bottom dielectric not being disposed over any portion of the mesa surface.

23. An apparatus, comprising:

a field-effect transistor (FET) region including;

a FET trench disposed in a semiconductor region and including a sidewall and a bottom portion,

a FET sidewall dielectric lining a sidewall of the FET trench,

a FET electrode disposed in the FET trench, and

a FET thick bottom dielectric lining the bottom portion of the FET trench, the FET thick bottom dielectric having a thickness different than a thickness of the FET sidewall dielectric; and

a non-field-effect transistor (FET) region including;

a non-FET trench disposed in the semiconductor region and including a sidewall and a bottom portion,

a non-FET sidewall dielectric lining a sidewall of the non-FET trench, and

a non-FET thick bottom dielectric lining the bottom portion of the non-FET trench, the non-FET thick bottom dielectric having a thickness different than a thickness of the non-FET sidewall dielectric.

24. The apparatus of claim 23, further comprising:

a Schottky diode in the non-FET region, the Schottky diode being associated with the non-FET trench, the non-FET sidewall dielectric, and the non-FET thick bottom dielectric.

25. The apparatus of claim 23, wherein the FET electrode is a gate electrode disposed in an upper portion of the trench,

the apparatus further comprising:

a FET shield electrode disposed in a lower portion of the FET trench.

26. The apparatus of claim 23, further comprising:

an interconnect layer functioning as an anode electrode of the non-FET region and as a source interconnect of a source region of the FET region.

27. The apparatus of claim 23, wherein the non-FET region is a first non-FET trench,

the apparatus further comprising:

a second non-FET trench, and

a mesa surface disposed between the first non-FET trench and the second non-FET trench; and

an interconnect layer disposed over the FET region and over the non-FET region such that the interconnect layer contacts the mesa surface and contacts a source region of the FET region.

28. The apparatus of claim 23, further comprising:

an interconnect layer disposed over the FET region and over the non-FET region such that the interconnect layer contacts a mesa surface included in the non-FET region to form a Schottky contact.

29. The apparatus of claim 23, wherein the thickness of the non-FET thick bottom dielectric is greater than the thickness of the non-FET sidewall dielectric.

30. The apparatus of claim 23, wherein the thickness of the FET thick bottom dielectric is greater than the thickness of the FET sidewall dielectric.