Method for design and manufacturing of a 3D semiconductor device

• US 8,669,778 B1
• Filed: 05/02/2011
• Issued: 03/11/2014
• Est. Priority Date: 04/14/2009
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Wurman, Zeev
• Primary Examiner(s): Tran, Thienvu
• Application Number:
  US13/098,997
• Time in Patent Office: 1,044 Days
• Field of Search: 326 37- 41, 326/47, 326/101, 716/104, 716/105
• US Class Current: 326/37
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/50 : having transistors on different levels, e.g. 3D ROM

Abstract

A method for the design and manufacturing of a 3D semiconductor device including a first circuit stratum and a second circuit stratum, the method including: applying a synthesis tool with at least first and second technology libraries; and performing a synthesis that utilizes the at least first and second technology libraries, where the first and second technology libraries correspond to two different processes, where the first technology library targets the first circuit stratum and the second technology library targets the second circuit stratum, and where the performing a synthesis results in a netlist, the netlist includes first cells of the first technology library and second cells of the second technology library.

Claims

1. A method for the design and manufacturing of a 3D semiconductor device comprising a first circuit stratum and a second circuit stratum, the method comprising:

applying a synthesis tool with at least first and second technology libraries; and

performing a synthesis that utilizes said at least first and second technology libraries,

wherein said first and second technology libraries correspond to two different processes,

wherein said first technology library targets said first circuit stratum and said second technology library targets said second circuit stratum,

wherein said first circuit stratum is fabricated using a less advanced process node than said second circuit stratum, and

wherein said performing a synthesis results in a netlist, said netlist comprises first cells of said first technology library and second cells of said second technology library.

2. A method according to claim 1 wherein said first circuit stratum could be made with a lithography tool lower in cost than a lithography tool for said second circuit stratum.

3. A method according to claim 1, further comprising:

placing cells synthesized using the first technology library on said first circuit stratum and cells synthesized using the second technology library on said second circuit stratum.

4. A method for the design and manufacturing of a 3D semiconductor device comprising a first circuit stratum and a second circuit stratum, the method comprising:

applying a synthesis tool with at least first and second technology libraries; and

performing a synthesis that utilizes said at least first and second technology libraries,

wherein said first and second technology libraries correspond to two different processes,

wherein said first technology library targets said first circuit stratum and said second technology library targets said second circuit stratum,

wherein said first circuit stratum is fabricated using a less advanced process node than said second circuit stratum,

wherein said performing a synthesis results in a netlist, said netlist comprises first cells of said first technology library and second cells of said second technology library, and

wherein said device empowers a mobile system.

5. A method according to claim 4 wherein said first circuit stratum could be made with a lithography tool lower in cost than a lithography tool for said second circuit stratum.

6. A method according to claim 4, further comprising:

placing cells synthesized using the first technology library on said first circuit stratum and cells synthesized using the second technology library on said second circuit stratum.

7. A method for the design and manufacturing of a 3D semiconductor device comprising a first circuit stratum and a second circuit stratum, the method comprising:

applying a synthesis tool with at least first and second technology libraries; and

performing a synthesis that utilizes said at least first and second technology libraries,

wherein said first and second technology libraries correspond to two different processes,

wherein said first technology library targets said first circuit stratum and said second technology library targets said second circuit stratum,

wherein said first circuit stratum is fabricated using a less advanced process node than said second circuit stratum,

wherein said performing a synthesis results in a netlist, said netlist comprises first cells of said first technology library and second cells of said second technology library, and

wherein said device is a monolithic 3D semiconductor device.

8. A method according to claim 7 wherein said first circuit stratum could be made with a lithography tool lower in cost than a lithography tool for said second circuit stratum.

9. A method according to claim 7, further comprising:

placing cells synthesized using the first technology library on said first circuit stratum and cells synthesized using the second technology library on said second circuit stratum.

10. A method according to claim 7 wherein said device empowers a mobile system.