Analog delay cells for the power supply of an RFID tag

• US 8,669,801 B2
• Filed: 06/06/2012
• Issued: 03/11/2014
• Est. Priority Date: 06/10/2011
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Ochoa, Agustin, Tang, Howard
• Primary Examiner(s): Luu, An
• Application Number:
  US13/490,267
• Publication Number:
  US 20130141151A1
• Time in Patent Office: 643 Days
• Field of Search: 327309-310, 327313-314, 327/318, 327327-328, 327/530, 327/532, 327/538, 327540-542, 361 56- 57, 361/91.1, 361/111
• US Class Current: 327/278
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: G06K 19/0715 the arrangement including means to regulate power transfer to the integrated circuit
• CPC Class Codes: H03H 11/26 Time-delay networks analogue shift registers G11C27/04
• CPC Class Codes: H03H 19/004 Switched capacitor networks

Abstract

A delay circuit for an RFID tag includes a power supply input and a power supply output and one or more delay circuits in cascade connection between the power supply input and the power supply output. A first delay circuit includes a passive circuit, a second delay circuit includes a ramp circuit, and a third delay circuit includes a current mirror circuit.

Claims

1. A delay circuit for a power supply comprising:

a power supply input and a power supply output;

a ramp circuit coupled between the power supply input and ground; and

a transistor having a current path coupled between the power supply input and the power supply output, and a control node coupled to an intermediate node of the ramp circuit,

wherein the ramp circuit comprises a capacitor and a bandgap (BGAP) current source in series connection.

2. The delay circuit of claim 1 wherein the capacitor is coupled between the power supply input and the intermediate node.

3. The delay circuit of claim 1 wherein the current source is coupled between the intermediate node and ground.

4. The delay circuit of claim 1 wherein the transistor comprises a P-channel transistor.

5. A delay circuit for a power supply comprising:

a power supply input and a power supply output;

a current mirror circuit having an input coupled to a bandgap (BGAP) current source connected between the input of the current mirror circuit and ground, an output coupled to the power supply output, and a power node coupled to the power supply input; and

a capacitor coupled between the power supply output and ground.

6. The delay circuit of claim 5 wherein the current mirror circuit comprises a two transistor current mirror.

7. The delay circuit of claim 5 wherein the current mirror circuit comprises an MOS current mirror.

8. The delay circuit of claim 5 wherein the current mirror circuit comprises first and second P-channel transistors.

9. The delay circuit of claim 5 wherein the current source comprises a temperature stabilized current source.

10. A delay circuit for an RFID tag comprising:

a power supply input and a power supply output; and

first and second delay circuits in cascade connection between the power supply input and the power supply output,

wherein the second delay circuit comprises;

a local power supply input and a local power supply output;

a current mirror circuit having an input coupled to a current source, an output coupled to the local power supply output, and a power node coupled to the local power supply input; and

a capacitor coupled between the local power supply output and ground.

11. The delay circuit of claim 10 wherein the first delay circuit comprises:

a local power supply input and a local power supply output;

a passive circuit coupled between the local power supply input and ground; and

a transistor having a current path coupled between the local power supply input and the local power supply output, and a control node coupled to an intermediate node of the passive circuit.

12. The delay circuit of claim 10 wherein the first delay circuit comprises:

a local power supply input and a local power supply output;

a ramp circuit coupled between the local power supply input and ground, the ramp circuit comprising a capacitor and a current source in series connection; and

a transistor having a current path coupled between the local power supply input and the local power supply output, and a control node coupled to an intermediate node of the ramp circuit.

13. The delay circuit of claim 12 wherein the current source comprises a temperature stabilized current source.

14. The delay circuit of claim 12 wherein the current source of the ramp circuit comprises a bandgap (BGAP) current source.

15. The delay circuit of claim 10 wherein at least one of the first or the second delay circuits comprises a P-channel transistor based delay circuit.

16. A delay circuit comprising:

a power supply input and a power supply output; and

a first delay circuit and a second delay circuit in cascade connection between the power supply input and the power supply output,

wherein the first delay circuit comprises a ramp circuit including a capacitor and a bandgap (BGAP) current source in series connection coupled between the power supply input and ground, and a transistor having a current path coupled between the power supply input and the power supply output, and a control node coupled to an intermediate node between the capacitor and current source of the ramp circuit.

17. The delay circuit of claim 16 wherein the current source of the ramp circuit comprises a temperature stabilized current source.

18. The delay circuit of claim 17 wherein the second delay circuit comprises:

a local power supply input and a local power supply output;

a current mirror circuit having an input coupled to a current source, an output coupled to the local power supply output, and a power node coupled to the local power supply input; and

a capacitor coupled between the local power supply output and ground.

19. The delay circuit of claim 18 wherein the current source of the second delay circuit comprises a temperature stabilized current source.

20. The delay circuit of claim 19 wherein the current mirror circuit comprises an MOS current mirror.