Asynchronous successive approximation register analog-to-digital converter and operating method thereof

• US 8,669,897 B1
• Filed: 11/05/2012
• Issued: 03/11/2014
• Est. Priority Date: 11/05/2012
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chen, Po-Hua, Cheng, Hsueh-Chen, Hsu, Wen-Hong, Liow, Yu-Yee
• Primary Examiner(s): Young, Brian
• Application Number:
  US13/668,339
• Time in Patent Office: 491 Days
• Field of Search: 341/155, 341/161, 341/163, 341/120
• US Class Current: 341/161
• CPC Class Codes: H03M 1/125 Asynchronous, i.e. free-running operation within each conversion cycle
• CPC Class Codes: H03M 1/462 Details of the control circuitry, e.g. of the successive approximation register

Abstract

An asynchronous successive approximation register analog-to-digital converter includes a clock generator, a logic control unit, a sample and hold circuit, a digital-to-analog converter and a comparator. The clock generator is used to generate a clock signal. The logic control unit is for generating a sample and hold clock according to the clock signal. The sample and hold circuit is for sampling an analog signal according to the sample and hold clock to obtain and hold a sampling signal. The digital-to-analog converter is for generating a reference value according to a digital value transmitted from the logic control unit. The comparator is for generating a comparison value according to the sampling signal and the reference value.

Claims

1. An asynchronous successive approximation register analog-to-digital converter comprising:

a clock generator for generating a clock signal according to an external clock, a frequency of the clock signal being higher than a frequency of the external clock;

a logic control unit coupled to the clock generator for generating a sample and hold clock according to the clock signal;

a sample and hold circuit coupled to the logic control unit for sampling an analog signal according to the sample and hold clock to obtain and hold a sampling signal;

a digital-to-analog converter coupled to the logic control unit for generating a reference value according to a digital value transmitted from the logic control unit;

a comparator coupled to the sample and hold circuit and the digital-to-analog converter for generating a comparison value according to the sampling signal and the reference value.

2. The asynchronous successive approximation register analog-to-digital converter of claim 1, further comprising a latch, coupled between the comparator and the logic control unit for latching the comparison value and outputting the comparison value to the logic control unit, so as to enable the logic control unit to output a next digital value according to the comparison value.

3. The asynchronous successive approximation register analog-to-digital converter of claim 1, wherein the logic control unit comprises a latch for latching the comparison value.

4. The asynchronous successive approximation register analog-to-digital converter of claim 1, wherein the sample and hold circuit comprises a capacitor.

5. The asynchronous successive approximation register analog-to-digital converter of claim 1, wherein the clock generator is a phase locked loop.

6. The asynchronous successive approximation register analog-to-digital converter of claim 1, wherein the clock generator comprises:

a differential voltage generator for generating a first set of differential voltages;

an amplifier coupled to the differential voltage generator for generating a second set of differential voltages according to the first set of differential voltages;

a latch coupled to the amplifier for generating a third set of differential voltages according to the second set of differential voltages;

a logic unit coupled to the latch for outputting a first logic signal according to whether two differential voltages of the third set of differential voltages are the same;

a counter for outputting a select signal according to the external clock and the clock signal;

a multiplexer, comprising;

a first input end coupled to the logic unit for receiving the first logic signal;

a second input end coupled to a ground end;

a select end coupled to the counter for receiving the select signal; and

an output end for outputting a second logic signal; and

a delay unit for adjusting a frequency of the second logic signal to generate the clock signal, comprising;

an input end coupled to the output end of the multiplexer for receiving the second logic signal; and

an output end coupled to the latch and the counter for outputting the clock signal.

7. The asynchronous successive approximation register analog-to-digital converter of claim 6, wherein the differential voltage generator comprises:

a first resistor having a first end coupled to a first voltage source;

a second resistor having a first end coupled to the first voltage source, a resistance of the second resistor being equal to a resistance of the first resistor;

a third resistor coupled between a second end of the first resistor and the ground end; and

a variable resistor coupled between a second end of the second resistor and the ground end.

8. The asynchronous successive approximation register analog-to-digital converter of claim 7, wherein the amplifier comprises:

a fourth resistor having a first end coupled to the first voltage source or a second voltage source, and a second end coupled to a first input end of the latch;

a fifth resistor having a first end coupled to the first voltage source or the second voltage source, and a second end coupled to a second input end of the latch, a resistance of the fourth resistor being equal to a resistance of the fifth resistor;

a first N type metal oxide semiconductor transistor comprising;

a drain coupled to the second end of the fourth resistor;

a source; and

a control end coupled to the second end of the second resistor for receiving a first voltage of the first set of differential voltages;

a second N type metal oxide semiconductor transistor having the same channel width-to-length ratio as the first N type metal oxide semiconductor transistor, comprising;

a drain coupled to the second end of the fifth resistor;

a source; and

a control end coupled to the second end of the first resistor for receiving a second voltage of the first set of differential voltages; and

a current source comprising;

a first end coupled to the source of the first N type metal oxide semiconductor transistor and the source of the second N type metal oxide semiconductor transistor; and

a second end coupled to the ground end.

9. The asynchronous successive approximation register analog-to-digital converter of claim 6, wherein the differential voltage generator comprises:

a first resistor having a first end coupled to a first voltage source; and

a second resistor having a first end coupled to the first voltage source, a resistance of the first resistor being equal to a resistance of the second resistor.

10. The asynchronous successive approximation register analog-to-digital converter of claim 9, wherein the amplifier comprises:

a third resistor having a first end coupled to the first voltage source or a second voltage source, and a second end coupled to a first input end of the latch;

a fourth resistor having a first end coupled to the first voltage source or the second voltage source, and a second end coupled to a second input end of the latch, a resistance of the fourth resistor being equal to a resistance of the third resistor;

a first N type metal oxide semiconductor transistor comprising;

a drain coupled to the second end of the third resistor;

a source; and

a control end coupled to the second end of the second resistor for receiving a first voltage of the first set of differential voltages;

at least one second N type metal oxide semiconductor transistor, each second N type metal oxide semiconductor transistor of the at least one second N type metal oxide semiconductor transistor comprising;

a drain coupled to the second end of the third resistor;

a source, coupled to the source of the first N type metal oxide semiconductor transistor; and

a control end coupled to the second end of the second resistor or the ground end;

a third N type metal oxide semiconductor transistor having the same channel width-to-length ratio as the first N type metal oxide semiconductor transistor, comprising;

a drain coupled to the second end of the fourth resistor;

a source; and

a control end coupled to the second end of the first resistor for receiving a second voltage of the first set of differential voltages; and

a current source, comprising;

a first end coupled to the source of the first N type metal oxide semiconductor transistor and the source of the third N type metal oxide semiconductor transistor; and

a second end coupled to the ground end.

11. A method for operating an asynchronous successive approximation register analog-to-digital converter, comprising:

generating a first set of differential voltages;

generating a second set of differential voltages according to the first set of differential voltages;

generating a third set of differential voltages according to the second set of differential voltages;

outputting a first logic signal according to whether two differential voltages of the third set of differential voltages are the same;

outputting a select signal according to an external clock and a clock signal;

outputting a second logic signal according to the first logic signal, a ground voltage and the select signal;

adjusting a frequency of the second logic signal to generate the clock signal according to an external clock, a frequency of the clock signal being higher than a frequency of the external clock;

generating a sample and hold clock according to the clock signal;

sampling an analog signal according to the sample and hold clock to obtain and hold a sampling signal;

generating a reference value according to a digital value; and

generating a comparison value according to the sampling signal and the reference value.

12. The method of claim 11, further comprising:

latching the comparison value.

13. The method of claim 12, further comprising:

outputting a next digital value according to the comparison value.