Reducing weak-erase type read disturb in 3D non-volatile memory

• US 8,670,285 B2
• Filed: 02/02/2012
• Issued: 03/11/2014
• Est. Priority Date: 02/02/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dong, Yingda, Mui, Man L, Miwa, Hitoshi
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Huang, Min
• Application Number:
  US13/364,518
• Publication Number:
  US 20130201760A1
• Time in Patent Office: 768 Days
• Field of Search: 365/206
• US Class Current: 365/206
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.

Claims

1. A method for performing a read operation in a 3D stacked non-volatile memory device comprising multiple levels of memory cells, the read operation is performed on selected memory cells in a selected level of the multiple levels, the method comprising:

increasing a pass voltage from an initial level to at least a first elevated level, for memory cells in unselected levels of the multiple levels, the memory cells in the multiple levels of memory cells are arranged in at least one selected string of memory cells and at least one unselected string of memory cells, the at least one selected string of memory cells includes at least one of the selected memory cells, and comprises a drain end with an associated first select gate and a source end with an associated second select gate, and the at least one unselected string of memory cells does not include any of the selected memory cells, and comprises a drain end with an associated third select gate and a source end with an associated fourth select gate;

during the increasing, providing the first select gate in a conductive state;

while providing the first select gate in the conductive state, transitioning at least one of the third or fourth select gates between a non-conductive state and the conductive state; and

applying a control gate read voltage to the selected memory cells, and sensing whether a threshold voltage of the at least one of the selected memory cells is above the control gate read voltage.

2. The method of claim 1, further comprising:

during the increasing, applying a voltage to the selected level which is sufficiently high to render the selected memory cells in the conductive state.

3. The method of claim 1, further comprising:

the transitioning comprises transitioning both the third and fourth select gates between the non-conductive state and the conductive state.

4. The method of claim 1, further comprising:

while providing the first select gate in the conductive state, transitioning the at least one of the third or fourth select gates from the conductive state back to the non-conductive state.

5. The method of claim 1, further comprising:

after the pass voltage reaches the at least a first elevated level, transitioning the at least one of the third or fourth select gates from the conductive state back to the non-conductive state.

6. The method of claim 5, further comprising:

increasing the pass voltage from the at least a first elevated level to a second elevated level, after the transitioning the at least one of the third or fourth select gates from the conductive state back to the non-conductive state.

7. The method of claim 1, further comprising:

while providing the first select gate in the conductive state, applying, via a common bit line, a non-zero voltage to the drain end of the at least one selected string of memory cells and to the drain end of the at least one unselected string of memory cells.

8. The method of claim 1, wherein:

the transitioning the at least one of the third or fourth select gates between the non-conductive state and the conductive state, comprises transitioning the third and fourth select gates from the non-conductive state to the conductive state; and

the method further comprises, while providing the first select gate in the conductive state, transitioning the third and fourth select gates from the conductive state back to the non-conductive state.

9. The method of claim 4, wherein:

the transitioning the at least one of the third or fourth select gates from the non-conductive state to the conductive state comprises increasing a voltage of the at least one of the third or fourth select gates, and the transitioning the at least one of the third or fourth select gates from the conductive state back to the non-conductive state comprises decreasing the voltage of the at least one of the third or fourth select gates.

10. The method of claim 9, wherein:

the voltage of the at least one of the third or fourth select gates has a spike shape such that the voltage of the at least one of the third or fourth select gates does not reach a steady state level after being increased and before being decreased.

11. The method of claim 9, wherein:

the voltage of the at least one of the third or fourth select gates reaches a steady state level after being increased and before being decreased.

12. A 3D stacked non-volatile memory device, comprising:

multiple levels of memory cells formed on a substrate, the memory cells in the multiple levels of memory cells comprise selected memory cells in a selected level of the multiple levels, and are arranged in at least one selected string of memory cells and at least one unselected string of memory cells, where (a) the at least one selected string of memory cells includes at least one of the selected memory cells, and comprises a drain end with an associated first select gate and a source end with an associated second select gate, and (b) the at least one unselected string of memory cells does not include any of the selected memory cells, and comprises a drain end with an associated third select gate and a source end with an associated fourth select gate; and

at least one control circuit, the at least one control circuit, to perform a read operation on the selected memory cells in the selected level of the multiple levels;

(c) increases a pass voltage from an initial level to at least a first elevated level, for memory cells in unselected levels of the multiple levels, (d) during the increase, provides the first select gate in a conductive state, (e) while the first select gate is provided in the conductive state, transitions at least one of the third or fourth select gates between a non-conductive state and the conductive state, (f) applies a control gate read voltage to the selected memory cells, and (g) with the control gate read voltage applied, senses whether a threshold voltage of the at least one of the selected memory cells is above the control gate read voltage.

13. The 3D stacked non-volatile memory device of claim 12, wherein:

during the increase, the at least one control circuit applies a voltage to the selected level which is sufficiently high to render the selected memory cells in the conductive state.

14. The 3D stacked non-volatile memory device of claim 12, wherein:

while the first select gate is provided in the conductive state, the at least one control circuit transitions the at least one of the third or fourth select gates from the conductive state back to the non-conductive state.

15. The 3D stacked non-volatile memory device of claim 12, wherein:

after the pass voltage reaches the at least a first elevated level, the at least one control circuit transitions the at least one of the third or fourth select gates from the conductive state back to the non-conductive state.

16. The 3D stacked non-volatile memory device of claim 15, wherein:

the at least one control circuit increases the pass voltage from the at least a first elevated level to a second elevated level, after the at least one of the third or fourth select gates is transitioned from the conductive state back to the non-conductive state.

17. The 3D stacked non-volatile memory device of claim 12, wherein:

the transitioning the at least one of the third or fourth select gates between the non-conductive state and the conductive state, comprises transitioning the third and fourth select gates from the non-conductive state to the conductive state; and

the at least one control circuit, while providing the first select gate in the conductive state, transitions the third and fourth select gates from the conductive state back to the non-conductive state.

18. The 3D stacked non-volatile memory device of claim 12, wherein:

each memory string comprises a U-shaped NAND string or a straight NAND string.

19. A method for performing a read operation in a 3D stacked non-volatile memory device comprising multiple levels of memory cells, the read operation is performed on selected memory cells in a selected level of the multiple levels, the method comprising:

boosting a channel of at least one unselected string of memory cells, the memory cells in the multiple levels of memory cells are arranged in at least one selected string of memory cells and the at least one unselected string of memory cells, the at least one selected string of memory cells includes at least one of the selected memory cells, comprises a drain end with an associated first select gate and a source end with an associated second select gate, and the at least one unselected string of memory cells does not include any of the selected memory cells, and comprises a drain end with an associated third select gate and a source end with an associated fourth select gate, the boosting the channel includes increasing a pass voltage from an initial level to at least a first elevated level, for memory cells in unselected levels of the multiple levels;

during the increasing of the pass voltage, before the pass voltage reaches the first elevated level, interrupting the boosting by raising a voltage of the first select gate to cause the first select gate to transition to a conductive state; and

with the channel at a boosted level caused by the boosting, and the pass voltage at the at least the first elevated level;

applying a control gate read voltage to the selected memory cells, and sensing whether a threshold voltage of the at least one of the selected memory cells is above the control gate read voltage.

20. The method of claim 19, further comprising:

continuing to apply the pass voltage at the at least the first elevated level during the applying the control gate read voltage and during the sensing.