Simulating a memory standard

• US 8,671,244 B2
• Filed: 07/13/2011
• Issued: 03/11/2014
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Le, Vu
• Application Number:
  US13/181,747
• Publication Number:
  US 20120011310A1
• Time in Patent Office: 972 Days
• Field of Search: 711/105, 711/110, 711/167, 711/170, 711/171, 711/172
• US Class Current: 711/105
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept and defines a first version of a protocol. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard. The second different memory standard defines a second set of control signals that the emulated second memory circuit is operable to accept and defines a second different version of a protocol. Both the first version of the protocol and the second different version of the protocol are associated either with DDR2 dynamic random access memory (DRAM) or with DDR3 DRAM.

Claims

1. An apparatus comprising:

a plurality of first memory circuits, each first memory circuit of the plurality of first memory circuits being associated with a first memory standard, where the first memory standard defines a behavior and timing of a first set of control signals that each first memory circuit is operable to accept; and

an interface circuit coupled to the plurality of first memory circuits, the interface circuit being operable to emulate a second set of control signals that at least one second memory circuit associated with a second different memory standard is operable to accept, such that the plurality of first memory circuits appear to a host system as the at least one second memory circuit,

wherein a behavior and timing of the second set of control signals are defined by the second different memory standard,

the first memory standard further defines a first version of a protocol, and the second different memory standard further defines a second different version of the protocol, and

both of the first version of the protocol and the second different version of the protocol are associated either with DDR2 dynamic random access memory (DRAM) or with DDR3 DRAM.

2. The apparatus of claim 1, where the first memory standard further defines, for each first memory circuit of the plurality of first memory circuits, a first memory behavior that is responsive to the first set of control signals, and where the second different memory standard further defines, for the at least one second memory circuit, a second memory behavior that is responsive to the second set of control signals.

3. The apparatus of claim 1, where the first memory standard is associated with a first memory capacity, and where the second different memory standard is associated with a second different memory capacity.

4. The apparatus of claim 3, where the second memory capacity is greater than the first memory capacity.

5. The apparatus of claim 1, where the interface circuit includes a buffer.

6. The apparatus of claim 1, where the interface circuit includes a register.

7. The apparatus of claim 1, further comprising a dual in-line memory module (DIMM), where the plurality of first memory circuits are coupled to the DIMM.

8. The apparatus of claim 1, where the interface circuit is coupled to the DIMM.

9. The apparatus of claim 1, where the interface circuit includes a first component and a second component, and where the first component is operable to:

receive address and control signals from a host system; and

send at least one of the control signals received from the host system to the second component.

10. The apparatus of claim 9, where the second component is operable to send to the plurality of memory circuits the at least one control signal received from the first component.

11. The apparatus of claim 10, where the second component is operable to receive data signals from the host system and send the data signals received from the host system to the plurality of first memory circuits.

12. The apparatus of claim 11, where the second component is operable to delay sending the at least one control signal or the data signals to the plurality of first memory circuits.

13. The apparatus of claim 1, where the first version of a protocol defines a first latency timing and the second different version of the protocol defines a second different latency timing.