Microprocessor that fetches and decrypts encrypted instructions in same time as plain text instructions
First Claim
1. A microprocessor, comprising:
- an instruction cache;
an instruction decode unit; and
a fetch unit, configured to;
(a) fetch a block of instruction data from the instruction cache;
(b) perform a Boolean exclusive-OR (XOR) operation on the block with a data entity to generate plain text instruction data; and
(c) provide the plain text instruction data to the instruction decode unit;
wherein in a first instance the block comprises encrypted instruction data and the data entity is a decryption key;
wherein in a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes;
wherein the microprocessor is configured to use equal amounts of time to perform feats (a), (b), and (c) in the first and second instances regardless of whether the block of instruction data is encrypted or unencrypted;
wherein the plain text instruction data decrypted from the encrypted instruction data is unobservable outside the microprocessor; and
wherein the time to perform said feats (a), (b), and (c) is the same independent of whether a branch instruction is present or absent within the fetched block of instruction data.
1 Assignment
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Accused Products
Abstract
A fetch unit (a) fetches a block of instruction data from an instruction cache of the microprocessor; (b) performs an XOR on the block with a data entity to generate plain text instruction data; and (c) provides the plain text instruction data to an instruction decode unit. In a first instance the block comprises encrypted instruction data and the data entity is a decryption key. In a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes. The time required to perform (a), (b), and (c) is the same in the first and second instances regardless of whether the block is encrypted or unencrypted. A decryption key generator selects first and second keys from a plurality of keys, rotates the first key, and adds/subtracts the rotated first key to/from the second key, all based on portions of the fetch address, to generate the decryption key.
46 Citations
22 Claims
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1. A microprocessor, comprising:
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an instruction cache; an instruction decode unit; and a fetch unit, configured to; (a) fetch a block of instruction data from the instruction cache; (b) perform a Boolean exclusive-OR (XOR) operation on the block with a data entity to generate plain text instruction data; and (c) provide the plain text instruction data to the instruction decode unit; wherein in a first instance the block comprises encrypted instruction data and the data entity is a decryption key; wherein in a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes; wherein the microprocessor is configured to use equal amounts of time to perform feats (a), (b), and (c) in the first and second instances regardless of whether the block of instruction data is encrypted or unencrypted; wherein the plain text instruction data decrypted from the encrypted instruction data is unobservable outside the microprocessor; and wherein the time to perform said feats (a), (b), and (c) is the same independent of whether a branch instruction is present or absent within the fetched block of instruction data. - View Dependent Claims (2, 3, 4)
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5. A microprocessor, comprising:
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an instruction cache; an instruction decode unit; and a fetch unit, configured to; (a) fetch a block of instruction data from the instruction cache; (b) perform a Boolean exclusive-OR (XOR) operation on the block with a data entity to generate plain text instruction data; and (c) provide the plain text instruction data to the instruction decode unit; wherein in a first instance the block comprises encrypted instruction data and the data entity is a decryption key; wherein in a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes; wherein the microprocessor is configured to use equal amounts of time to perform feats (a), (b), and (c) in the first and second instances regardless of whether the block of instruction data is encrypted or unencrypted; wherein to fetch the block of instruction data from the instruction cache the fetch unit is configured to apply a fetch address to the instruction cache, wherein the fetch unit if further configured to generate the decryption key as a function of a portion of the fetch address and a plurality of key values within a time required to fetch the block of instruction data from the instruction cache. - View Dependent Claims (6, 7, 8)
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9. A microprocessor, comprising:
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an instruction cache; an instruction decode unit; and a fetch unit, configured to; (a) fetch a block of instruction data from the instruction cache; (b) perform a Boolean exclusive-OR (XOR) operation on the block with a data entity to generate plain text instruction data; and (c) provide the plain text instruction data to the instruction decode unit; wherein in a first instance the block comprises encrypted instruction data and the data entity is a decryption key; wherein in a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes; wherein the microprocessor is configured to use equal amounts of time to perform feats (a), (b), and (c) in the first and second instances regardless of whether the block of instruction data is encrypted or unencrypted; wherein the fetch unit comprises; a control bit, configured to store an indication of whether the fetch unit is in a decryption mode or a plain text mode; a multiplexer, comprising; an output; a first data input configured to receive the decryption key; a second data input, configured to receive the Boolean zeroes; and a selection control input, configured to receive the value of the control bit and to cause the decryption key to be provided on the output when the value of the control bit indicates the decryption mode in the first instance and to cause the Boolean zeroes to be provided on the output when the value of the control bit indicates the plain text mode in the second instance; and an XOR gate, comprising; a first data input, configured to the output of the multiplexer; a second data input, configured to receive the fetched block of instruction data; and an output, coupled to the instruction decode unit for providing the plain text instruction data which is the Boolean XOR of the first and second data inputs. - View Dependent Claims (10, 11, 12)
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13. A method for operating a microprocessor having an instruction cache, the method comprising the following computer-implemented steps:
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(a) fetching a block of instruction data from the instruction cache; (b) performing a Boolean exclusive-OR (XOR) operation on the block with a data entity for generating plain text instruction data; and (c) providing the plain text instruction data to an instruction decode unit; wherein in a first instance the block comprises encrypted instruction data and the data entity is a decryption key; wherein in a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes; wherein the microprocessor is configured to use equal amounts of time to perform said feats (a), (b), and (c) in the first and second instances regardless of whether the block of instruction data is encrypted or unencrypted; wherein the plain text instruction data decrypted from the encrypted instruction data is unobservable outside the microprocessor; and wherein the time to perform said feats (a), (b), and (c) is the same independent of whether a branch instruction is present or absent within the fetched block of instruction data. - View Dependent Claims (14, 15, 16, 17)
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18. A method for operating a microprocessor having an instruction cache, the method comprising the following computer-implemented steps:
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(a) fetching a block of instruction data from the instruction cache by applying a fetch address to the instruction cache; (b) performing a Boolean exclusive-OR (XOR) operation on the block with a data entity for generating plain text instruction data; and (c) providing the plain text instruction data to an instruction decode unit; wherein in a first instance the block comprises encrypted instruction data and the data entity is a decryption key, which is generated as a function of a portion of the fetch address and a plurality of key values; wherein in a second instance the block comprises unencrypted instruction data and the data entity is Boolean zeroes; wherein the microprocessor is configured to use equal amounts of time to perform said feats (a), (b), and (c) in the first and second instances regardless of whether the block of instruction data is encrypted or unencrypted; wherein said generating the decryption key is performed within a time required to perform said fetching the block of instruction data from the instruction cache. - View Dependent Claims (19, 20, 21, 22)
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Specification