Dynamic frequency control using coarse clock gating

• US 8,671,380 B2
• Filed: 03/26/2012
• Issued: 03/11/2014
• Est. Priority Date: 07/18/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wang, James, Law, Patrick Y.
• Primary Examiner(s): Chiang, Jack
• Assistant Examiner(s): Ngo, Brian
• Application Number:
  US13/429,800
• Publication Number:
  US 20130021072A1
• Time in Patent Office: 715 Days
• Field of Search: 706/104, 706/133, 706/134, 327/291, 327/158, 327/161, 327/172, 327/173, 327/174, 327/175, 327/176, 327/124, 327/155, 713/320, 713/322, 713/324, 713/400, 713/500, 713/600
• US Class Current: 716/133
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H03K 23/66 with a variable counting base, e.g. by presetting or by adding or suppressing pulses
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.

Claims

1. An apparatus comprising:

a clock tree coupled to distribute a clock signal to each of a plurality of leaf nodes, wherein each leaf node is coupled to one or more synchronous circuits;

a plurality of fine-grain clock gating units, wherein each of the plurality of fine-grain clock gating units is configured to gate the clock signal provided to each of the one or more synchronous circuits of a corresponding one of the plurality of leaf nodes;

a functional unit including a number of the plurality of fine-grain clock gating units in a subset of the plurality of leaf nodes;

a coarse clock gating unit configured to gate the clock signal for each of the subset of the plurality of leaf nodes;

a gating control unit coupled to the coarse clock gating unit, wherein the gating control unit is configured to selectively control a frequency of the clock signal provided to each of the subset of the plurality of leaf nodes by enabling one of every N cycles of the clock signal and inhibiting N-1 of every N cycles of the clock signal, wherein N is an integer value that is greater than one; and

wherein the gating control unit is configured to dynamically change the frequency without suspending operation of the functional unit.

2. The apparatus as recited in claim 1, further comprising a clock generation unit configured to generate the clock signal.

3. The apparatus as recited in claim 1, wherein the gating control unit is further coupled to provide respective enable signals to each of the fine-grain clock gating units, wherein each of the fine-grain clock units is configured to provide the clock signal to respectively coupled synchronous circuits when its respective enable signal is asserted, and further configured to inhibit the clock signal from being provided to the respectively coupled synchronous circuits when its respective enable signal is de-asserted.

4. The apparatus as recited in claim 1, wherein the synchronous circuits includes at least one flop circuit and at least one latch.

5. The apparatus as recited in claim 1, wherein the coarse clock-gating unit and each of the fine-grain clock gating units includes a latch coupled to receive the enable signal and the clock signal, and an AND gate having a first input coupled to receive the enable signal from the latch and a second input coupled to receive the clock signal.

6. A method comprising:

providing a first clock signal to a coarse clock-gating unit, wherein the coarse clock gating unit is coupled to distribute a second clock signal that is based on the first clock signal to a plurality of leaf nodes of a clock tree, wherein each of the leaf nodes is associated with a corresponding fine-grain clock gating unit coupled to distribute, when enabled, the clock signal to each of a corresponding one or more synchronous circuits within a functional unit, each functional unit including a number of the fine-grain clock gating units in a subset of the plurality of leaf nodes, wherein the first clock signal has a first frequency and the second clock signal has a second clock frequency;

providing a coarse-gating enable signal to the coarse clock-gating unit, wherein the coarse clock gating unit is configured to output the second clock signal when the coarse-gating enable signal is asserted and is further configured to inhibit the second clock signal when the coarse-gating enable signal is de-asserted;

causing the second clock frequency to be less than the first clock frequency by asserting the coarse-gating enable signal for one of every N cycles of the first clock signal and de-asserting the coarse-gating enable signal for every N-1 cycles of the first clock signal, wherein N is an integer value greater than one; and

dynamically changing, by the coarse clock gating unit, the second frequency from being equal to the first clock frequency to being less than the first clock frequency.

7. The method as recited in claim 6 further comprising a clock generation unit generating the first clock signal and providing the first clock signal to the clock tree.

8. The method as recited in claim 6, further comprising causing the first clock frequency and the second clock frequency to be equal by asserting the coarse-clock gating enable signal for each cycle of the first clock signal.

9. The method as recited in claim 6 further comprising:

continuing operation of the functional unit during said dynamically changing the second clock frequency.

10. The method as recited in claim 9, further comprising:

reducing the second clock frequency from being equal to the first clock frequency responsive to a reduction in a processing workload of the functional block; and

increasing the second clock frequency to being equal to the first clock frequency responsive to an increase in the processing workload of the functional block.

11. A method comprising:

providing a root clock signal at a first frequency to a clock-gating unit;

outputting an operational clock signal from the clock-gating unit, wherein the operational clock signal is based on the root clock signal;

providing an enable signal to the clock-gating unit;

providing the operational clock signal to a functional block that includes a number of fine-grain clock gating units in a plurality of leaf nodes of a clock tree for the root clock signal;

dynamically changing, by the clock-gating unit, the second frequency without suspending operation of the functional block;

outputting the operational clock signal at the first frequency by asserting the enable signal for each of the cycles of the root clock signal; and

outputting the operational clock signal at a second frequency that is less than the first frequency by asserting the enable signal for one of every N cycles of the root clock signal and de-asserting the enable signal for N-1 of every N cycles of the root clock signal, wherein N is an integer greater than one.

12. The method as recited in claim 11, further comprising:

changing a frequency of the operational clock signal from the first frequency to the second frequency responsive to a reduction in a workload of the functional block; and

changing the frequency of the operational clock signal from the second frequency to the first frequency responsive to an increase in the workload of the functional block.

13. The method as recited in claim 11, further comprising:

a first clock gating unit receiving the root clock signal and providing a first operational clock signal at the second frequency to a first functional block;

a second clock gating unit receiving the root clock signal and providing a second operational clock signal at the second frequency to a second functional block; and

a clock control unit asserting a first enable signal to the first clock gating unit and a second enable signal to the second clock gating unit on a same cycle of the root clock signal.

14. An integrated circuit comprising:

a clock generation unit configured generate a global clock signal;

a plurality of functional units, wherein each of the plurality of functional units includes a number of fine-grain clock gating units in a plurality of leaf nodes of a clock tree for the global clock signal;

a plurality of clock gating units, wherein each of the plurality of clock gating units is coupled to a corresponding one of the plurality of functional units, wherein each of the plurality of clock gating units is coupled to receive the global clock signal and is configured to provide a corresponding operating clock signal to its corresponding functional unit; and

a clock control unit coupled to provide a corresponding one of a plurality of enable signals to each of the plurality of clock gating units, wherein each of the clock gating units is enabled to provide its respective operating clock signal to its respective functional unit when its respectively received enable signal is asserted;

wherein the clock control unit is further configured to dynamically change a frequency of each of the operating clock signals by alternately asserting and de-asserting the enable signals provided to each of the clock gating units, and wherein the clock control unit is configured to assert selected ones of the plurality of enable signals for one of every N cycles of the global clock signal and to de-assert the selected ones of the plurality of enable signals for N-1 of every N cycles of the global clock signal, wherein N is an integer value that is greater than one.

15. The integrated circuit as recited in claim 14, wherein each of the clock gating units is configured to:

provide its respective operating clock signal at a same frequency as that of the global clock signal when its respectively received enable signal is held asserted;

provide its respective operating clock signal at a frequency less than that of the global clock signal when its respectively received enable clock signal is alternately asserted and de-asserted.

16. The integrated circuit as recited in claim 14, wherein the clock gating unit is configured to selectively assert and de-assert each of the plurality of enable signals independently of one another.

17. The integrated circuit as recited in claim 14, wherein the clock control unit is configured to assert a first and second enable signals provided to first and second ones of the plurality of clock gating units on a same one of every N cycles of the global clock signal.

18. A system comprising:

a first functional unit and a second functional unit;

a clock generation unit configured to generate a global clock signal, wherein each of the first functional unit and the second functional unit include a number fine-grain clock gating units in a plurality of leaf nodes of a clock tree for the global clock signal;

a first clock gating unit coupled to receive the global clock signal and to provide a first clock signal to the first functional unit;

a second clock gating unit coupled to receive the global clock signal and to provide a second clock signal to the second functional unit;

a clock control unit coupled to provide a first enable signal to the first clock gating unit and a second enable signal to the second clock gating unit, wherein the clock control unit is configured to dynamically change respective frequencies of the first and second clock signals by selectively asserting and de-asserting the first and second enable signals, respectively, wherein a given one of the first and second clock gating units is configured to provide the corresponding one of first and second clock signals at a frequency that is 1/N of the frequency of the global clock signal responsive to the clock control unit asserting the corresponding one of the first and second enable signals for one of every N cycles of the global clock signal and de-asserting the corresponding one of the of the first and second enable signals for N-1 of every N cycles of the global clock signal, wherein N is an integer value that is greater than one.

19. The system as recited in claim 18, wherein the first and second clock gating units are configured to provide the first and second clock signals at a frequency equivalent to a frequency of the global clock signal when the first and second enable signals are held asserted.

20. The system as recited in claim 18, wherein the first and second functional units are configured to continue operations without suspension during a change of frequency of the first and second clock signals, respectively.

21. The system as recited in claim 18, wherein the clock control unit is configured to assert and de-assert the first enable signal independent of assertion and de-assertion of the second enable signal.