Multithreaded kernel for graphics processing unit

• US 8,671,411 B2
• Filed: 01/15/2010
• Issued: 03/11/2014
• Est. Priority Date: 02/18/2003
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Gosalia, Anuj B., Pronovost, Steve
• Primary Examiner(s): TO, JENNIFER N
• Application Number:
  US12/657,278
• Publication Number:
  US 20100122259A1
• Time in Patent Office: 1,516 Days
• Field of Search: 718/103
• US Class Current: 718/104
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and methods are provided for scheduling the processing of a coprocessor whereby applications can submit tasks to a scheduler, and the scheduler can determine how much processing each application is entitled to as well as an order for processing. In connection with this process, tasks that require processing can be stored in physical memory or in virtual memory that is managed by a memory manager. The invention also provides various techniques of determining whether a particular task is ready for processing. A “run list” may be employed to ensure that the coprocessor does not waste time between tasks or after an interruption. The invention also provides techniques for ensuring the security of a computer system, by not allowing applications to modify portions of memory that are integral to maintaining the proper functioning of system operations.

Claims

1. An apparatus for supporting scheduling of tasks for processing by a coprocessor, comprising:

a graphics coprocessor;

one or more applications that generate rendering tasks for processing by the coprocessor, wherein the rendering tasks are first stored in a user mode command buffer, and wherein the rendering tasks are stored in a per-application context in the user mode command buffer; and

a scheduler process that;

determines an order in which the rendering tasks are processed,

wherein the order accounts for any relative priority among a first application context relating to a first set of rendering tasks and one or more other application contexts relating to additional rendering tasks,

wherein the order accounts for a corresponding amount of processing time to which the first application and the one or more other applications are entitled, and

wherein the order is determined solely by the scheduler process; and

determines that there is insufficient supplemental memory to process a first rendering task from among the rendering tasks, and,

in response splits a buffer comprising rendering commands associated with the first rendering task by storing a first subset of a plurality of memory resources associated with the first rendering task in a first buffer and storing a second subset of the plurality of memory resources associated with the first rendering task in a second buffer.

2. An apparatus according to claim 1 wherein the scheduler process further determines a resource identifier for each memory resource of the plurality of memory resources.

3. An apparatus according to claim 1 wherein the graphics coprocessor supports interruption during the processing of a task by automatically saving task information to a coprocessor-accessible memory location.

4. An apparatus according to claim 3, further comprising at least one of a private address space for one or more rendering tasks, a private ring buffer where rendering tasks are accumulated, and a private piece of graphics coprocessor-accessible memory where a hardware state is saved when a rendering task is not being processed.

5. An apparatus according to claim 1 wherein the graphics coprocessor is capable of storing information regarding the history of graphics coprocessor switches from rendering task to rendering task in a specified system memory location readable by the scheduler process.

6. An apparatus according to claim 5 wherein the graphics coprocessor specifies a base address for the system memory location prior to storing information regarding the history of graphics coprocessor switches from rendering task to rendering task in the system memory location.

7. An apparatus according to claim 5 wherein the graphics coprocessor specifies a size for the system memory location prior to storing information regarding the history of graphics coprocessor switches from rendering task to rendering task in the system memory location.

8. An apparatus according to claim 5 wherein the graphics coprocessor specifies a write pointer for indicating where in the system memory location the graphics coprocessor should write to next.

9. An apparatus according to claim 1 wherein the graphics coprocessor supports fence instructions that cause the graphics coprocessor to write a piece of data associated with a fence instruction at an address specified in the fence instruction.

10. An apparatus according to claim 1 wherein the graphics coprocessor supports trap instructions that are capable of generating a central processing unit interrupt when processed by the graphics coprocessor.

11. An apparatus according to claim 1 wherein the graphics coprocessor supports enable/disable context switching instructions such that when context switching is disabled, the graphics coprocessor will not switch away from a current coprocessor task.

12. A method of scheduling of tasks for processing by a graphics coprocessor, comprising:

generating, by one or more applications, rendering tasks for processing by the graphics coprocessor;

storing, in a per-application context, the one or more rendering tasks in a user mode command buffer;

determining, solely by a scheduler process, an order in which the rendering tasks are processed,

wherein the order accounts for any relative priority among a first application context relating to a first set of rendering tasks and one or more other application contexts relating to additional rendering tasks, and

wherein the order accounts for a corresponding amount of processing time to which the first application and the one or more other applications are entitled;

determining that there is insufficient supplemental memory to process a first rendering task from among the rendering tasks; and

in response to determining that there is insufficient supplemental memory to process the first rendering task, splitting a buffer comprising rendering commands associated with the first rendering task by storing a first subset of a plurality of memory resources associated with the first rendering task in a first buffer and storing a second subset of the plurality of memory resources associated with the first rendering task in a second buffer.

13. The method of claim 12, further comprising determining a resource identifier for each memory resource of the plurality of memory resources.

14. The method of claim 12, further comprising automatically saving rendering task information to a graphics coprocessor-accessible memory location.

15. The method of claim 14, further comprising allocating at least one of a private address space for one or more rendering tasks, a private ring buffer where rendering tasks are accumulated, and a private piece of graphics coprocessor-accessible memory where a hardware state is saved when a rendering task is not being processed.

16. The method of claim 12, further comprising storing, by the graphics coprocessor, information regarding the history of graphics coprocessor switches from rendering task to rendering task in a system memory location readable by the scheduler process.

17. The method of claim 16, further comprising specifying, by the graphics coprocessor, a base address for the system memory location prior to storing information regarding the history of graphics coprocessor switches from rendering task to rendering task in the system memory location.

18. The method of claim 16, further comprising specifying, by the graphics coprocessor, a size for the system memory location prior to storing information regarding the history of graphics coprocessor switches from rendering task to rendering task in the system memory location.

19. The method of claim 16, further comprising specifying, by the graphics coprocessor, a write pointer for indicating where in the system memory location the graphics coprocessor should write to next.

20. The method of claim 12, further comprising receiving, at the graphics coprocessor, fence instructions that cause the graphics coprocessor to write a piece of data associated with a fence instruction at an address specified in the fence instruction.

21. The method of claim 12, further comprising receiving, at the graphics coprocessor, trap instructions that cause the graphics coprocessor to generate a central processing unit interrupt when processed by the graphics coprocessor.

22. The method of claim 12, further comprising receiving, at the graphics coprocessor, enable/disable context switching instructions such that when context switching is disabled, the graphics coprocessor will not switch away from a current coprocessor task.

23. A computer memory comprising computer-executable instructions for scheduling tasks for processing by a graphics coprocessor, the computer-executable instructions comprising instructions for:

generating, by one or more applications, rendering tasks for processing by the graphics coprocessor;

storing, in a per-application context, the one or more rendering tasks in a user mode command buffer;

determining, solely by a scheduler process, an order in which the rendering tasks are processed,

wherein the order accounts for any relative priority among a first application context relating to a first set of rendering tasks and one or more other application contexts relating to additional rendering tasks, and

wherein the order accounts for a corresponding amount of processing time to which the first application and the one or more other applications are entitled;

determining that there is insufficient supplemental memory to process a first rendering task from among the rendering tasks; and

in response to determining that there is insufficient supplemental memory to process the first rendering task, splitting a buffer commands associated with the first rendering task by storing a first subset of a plurality of memory resources associated with the first rendering task into a first buffer and storing a second subset of the plurality of memory resources associated with the first rendering task into a second buffer.

24. The computer memory of claim 23, further comprising instructions for determining a resource identifier for each memory resource of the plurality of memory resources.

25. The computer memory of claim 23, further comprising instructions for automatically saving rendering task information to a graphics coprocessor-accessible memory location.

26. The computer memory of claim 25, further comprising instructions for allocating at least one of a private address space for one or more rendering tasks, a private ring buffer where rendering tasks are accumulated, and a private piece of coprocessor-accessible memory where a hardware state is saved when a rendering task is not being processed.

27. The computer memory of claim 23, further comprising instructions for storing information regarding the history of graphics coprocessor switches from rendering task to rendering task in a system memory location readable by the scheduler process.

28. The computer memory of claim 27, further comprising instructions for specifying a base address for the system memory location prior to storing information regarding the history of graphics coprocessor switches from rendering task to rendering task in the system memory location.

29. The computer memory of claim 27, further comprising instructions for specifying a size for the system memory location prior to storing information regarding the history of graphics coprocessor switches from rendering task to rendering task in the system memory location.

30. The computer memory of claim 27, further comprising instructions for specifying a write pointer for indicating where in the system memory location the graphics coprocessor should write to next.

31. The computer memory of claim 23, further comprising instructions for receiving fence instructions that cause the graphics coprocessor to write a piece of data associated with a fence instruction at an address specified in the fence instruction.

32. The computer memory of claim 23, further comprising instructions for receiving trap instructions that cause the graphics coprocessor to generate a central processing unit interrupt when processed by the graphics coprocessor.

33. The computer memory of claim 23, further comprising instructions for receiving enable/disable context switching instructions such that when context switching is disabled, the graphics coprocessor will not switch away from a current graphics coprocessor task.

34. A computing device comprising computer-executable instructions for scheduling tasks for processing by a graphics coprocessor, the computer-executable instructions comprising instructions for:

generating, by one or more applications, rendering tasks for processing by the graphics coprocessor;

storing, in a per-application context, the one or more rendering tasks in a user mode command buffer;

determining, solely by a scheduler process, an order in which the rendering tasks are processed,

wherein the order accounts for any relative priority among a first application context relating to a first set of rendering tasks and one or more other application contexts relating to additional rendering tasks, and

wherein the order accounts for a corresponding amount of processing time to which the first application and the one or more other applications are entitled;

determining that there is insufficient supplemental memory to process a first rendering task from among the rendering tasks; and

in response to determining that there is insufficient supplemental memory to process the first rendering task, splitting a buffer commands associated with the first rendering task by storing a first subset of a plurality of memory resources associated with the first rendering task into a first buffer and storing a second subset of the plurality of memory resources associated with the first rendering task into a second buffer.