Superjunction structures for power devices and methods of manufacture

• US 8,673,700 B2
• Filed: 04/27/2011
• Issued: 03/18/2014
• Est. Priority Date: 04/27/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Rinehimer, Mark L., Shenoy, Praveen Muraleedharan
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): JONES, ERIC W
• Application Number:
  US13/095,678
• Publication Number:
  US 20120276701A1
• Time in Patent Office: 1,056 Days
• Field of Search: 438/270, 438/133, 438/156, 438/212, 257/302, 257/341, 257/E23.001, 257/E29.255
• US Class Current: 438/156
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

Claims

1. A method comprising:

forming an N-type epitaxial layer over a substrate;

forming a P-type body region in the N-type epitaxial layer;

forming planar gate electrodes extending adjacent to but being insulated from the N-type epitaxial layer by a gate dielectric;

after forming the P-type body region and the gate electrodes, forming a plurality of deep trenches extending in the N-type epitaxial layer, each of the plurality of deep trenches extending through the P-type body region and having a bottom surface disposed within the N-type epitaxial layer; and

filling the plurality of deep trenches with P-type silicon to form a plurality of P-pillars, portions of the N-type epitaxial layer separating the plurality of P-pillars forming N-pillars such that the P-pillars and the N-pillars form directly-adjacent pillars of alternating conductivity type, the P-pillars and the N-pillars being of substantially a same height.

2. The method of claim 1 further comprising:

forming, before forming the plurality of deep trenches, N-type source regions in the P-type body region.

3. The method of claim 1 further comprising:

after forming the plurality of deep trenches, forming a dielectric cap over each gate electrode, the dielectric caps defining contact openings between adjacent trenches from the plurality of deep trenches, the contact openings being formed over N-type source regions.

4. The method of claim 3 further comprising:

implanting P-type dopants into the P-type body regions through the contact openings to form P+ heavy body regions in the P-type body regions.

5. The method of claim 4 further comprising:

prior to forming the dielectric cap, forming a conformal layer that extends adjacent the gate electrodes such that the conformal layer spaces the P-type dopants implanted into the P-type body region from edges of the gate electrodes.

6. The method of claim 3 comprising:

etching a dimple in the P-type body region; and

implanting P-type dopants into the bottom of each dimple to form a heavy body region in the P-type body region.

7. The method of claim 6 further comprising:

forming a source metal layer electrically contacting the N-type source regions and the P+ heavy body region through the contact openings.

8. The method of claim 1, further comprising:

forming an active region and a termination region surrounding the active region, both the active region and the termination region including a plurality of P-pillars; and

prior to forming the P-type body region, forming a P-type Iso region in the N-type epitaxial layer in the termination region such that after the plurality of P-pillars are formed, the P-type Iso region connecting a predetermined number of the P-pillars in the termination region together.

9. The method of claim 8 further comprising:

forming a source metal layer electrically contacting the P-type Iso region.

10. The method of claim 1, wherein the forming the planar gate electrodes includes:

forming a gate dielectric layer over the N-type epitaxial layer; and

forming the planar gate electrodes over the gate dielectric layer, the planar gate electrodes being laterally spaced from one another, the plurality of deep trenches being formed between the planar gate electrodes.

11. An apparatus, comprising:

an epitaxial layer of a first conductivity type disposed over a substrate;

a body region of a second conductivity type disposed in the epitaxial layer;

a planar gate electrode extending adjacent to and insulated from the epitaxial layer by a gate dielectric; and

a plurality of trenches extending in the epitaxial layer, each trench from the plurality of trenches including a silicon of the second conductivity type to form a plurality of pillars of the second conductivity type, portions of the epitaxial layer separating the plurality of pillars of the second conductivity type forming directly-adjacent pillars of the first conductivity type such that the pillars of the first conductivity type alternate with the pillars of the second conductivity type, each of the plurality of trenches extending through the body region and terminating within the epitaxial layer, such that a discontinuity is defined in the body region, the pillars of the first conductivity type and the pillars of the second conductivity type being of substantially a same height.

12. The apparatus of claim 11, further comprising:

an active region; and

a termination region surrounding the active region, the active region including a first portion of the pillars of the second conductivity type and the termination region including a second portion of the plurality of pillars of the second conductivity type.

13. The apparatus of claim 12, further comprising an Iso region of the second conductivity type disposed in the epitaxial layer, the Iso region being disposed in the termination region such that at least two pillars of the second portion are electrically connected.

14. The apparatus of claim 13, further comprising a source metal layer electrically contacting the Iso region and a source region of the apparatus.

15. An apparatus, comprising:

an epitaxial layer of a first conductivity type disposed over a substrate;

a body region of a second conductivity type disposed in the epitaxial layer;

a planar gate electrode extending adjacent to and insulated from the epitaxial layer by a gate dielectric;

a first trench disposed in the epitaxial layer and including silicon of the second conductivity type disposed therein; and

a second trench disposed in the epitaxial layer and including a silicon of the second conductivity type disposed therein, the first trench and the second trench extending through the body region such that the body region is divided into a first portion, a second portion and a third portion, the first trench, the second trench and the epitaxial layer being of substantially a same height.

16. The apparatus of claim 15, further comprising, at least one source region of the first conductivity type disposed in the body region and adjacent to the gate electrode.

17. The apparatus of claim 15, further comprising:

a dimple disposed in the body region; and

a heavy body region disposed in the body region and disposed along a bottom surface of the dimple.

18. The apparatus of claim 15, further comprising a dielectric cap disposed over the gate electrode, the dielectric cap defining a contact opening over a source region of the first conductivity type, the contact opening being disposed between adjacent to the trench.

19. The apparatus of claim 18, further comprising a source metal layer electrically contacting the source region and the body region through the contact opening.