Methods of forming FinFET devices with alternative channel materials

• US 8,673,718 B2
• Filed: 07/09/2012
• Issued: 03/18/2014
• Est. Priority Date: 07/09/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Maszara, Witold P., Jacob, Ajey P., LiCausi, Nicholas V., Fronheiser, Jody A., Akarvardar, Kerem
• Primary Examiner(s): Fan, Michele
• Application Number:
  US13/544,259
• Publication Number:
  US 20140011341A1
• Time in Patent Office: 617 Days
• Field of Search: 438/268, 438/269, 257/E21.001, 257/E21.409, 257/E21.442
• US Class Current: 438/268
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

One method involves providing a substrate comprised of first and second semiconductor materials, performing an etching process through a hard mask layer to define a plurality of trenches that define first and second portions of a fin for a FinFET device, wherein the first portion is the first material and the second portion is the second material, forming a layer of insulating material in the trenches, performing a planarization process on the insulating material, performing etching processes to remove the hard mask layer and reduce a thickness of the second portion, thereby defining a cavity, performing a deposition process to form a third portion of the fin on the second portion, wherein the third portion is a third semiconducting material that is different from the second material, and performing a process such that a post-etch upper surface of the insulating material is below an upper surface of the third portion.

Claims

1. A method of forming a FinFET device, comprising:

providing a substrate comprised of a first semiconductor material;

performing a first epitaxial deposition process to form a layer of a second semiconductor material above said substrate;

forming a patterned hard mask layer above said layer of second semiconductor material;

performing a first etching process through said patterned hard mask layer to define a plurality of spaced-apart trenches that define first and second portions of a fin for said FinFET device, said first portion being comprised of said first semiconductor material, said second portion being comprised of said second semiconductor material;

forming a layer of insulating material in said trenches, said layer of insulating material overfilling said trenches and said patterned hard mask layer;

performing a planarization process on said layer of insulating material that exposes said patterned hard mask layer positioned above said second portion of said fin;

performing at least one second etching process to remove said patterned hard mask layer positioned above said second portion of said fin to thereby expose an upper surface of said second portion of said fin;

performing at least one third etching process to reduce a thickness of said second portion of said fin and thereby define a cavity within said layer of insulating material above said second portion of said fin;

performing a second epitaxial deposition process to form a third portion of said fin on said second portion of said fin within said cavity, said third portion of said fin being comprised of a third semiconductor material that is different than said second semiconductor material; and

performing a fourth etching process on said layer of insulating material such that a post-etch upper surface of said layer of insulating material after performing said fourth etching process is performed is below an upper surface of said third portion of said fin.

2. The method of claim 1, wherein said first semiconductor material is comprised of silicon, said second semiconductor material is comprised of one of silicon, silicon/germanium, germanium, a III-V material, a II-VI material, or a combination thereof, and said third semiconductor material is comprised of one of silicon, silicon/germanium, germanium, a III-V material, a II-VI material, or a combination thereof.

3. The method of claim 1, wherein said first semiconductor material is comprised of silicon, and said second semiconductor material is comprised of silicon/germanium with a germanium concentration of 1-99%, and said third semiconductor material is comprised of one of silicon, silicon/germanium, germanium, a III-V material, a II-VI material, or a combination thereof.

4. The method of claim 1, wherein said portion of said third portion of said fin that is positioned above said post-etch upper surface of said layer of insulating material defines a final fin height of said FinFET device.

5. The method of claim 1, wherein said post-etch, upper surface of said layer of insulating material is positioned above an upper surface of said second portion of said fin.

6. The method of claim 1, wherein said post-etch, upper surface of said layer of insulating material is positioned below an upper surface of said second portion of said fin.

7. The method of claim 1, wherein performing said planarization process comprises performing a chemical mechanical polishing process.

8. The method of claim 1, wherein said patterned hard mask layer is comprised of a layer of silicon dioxide and a layer of silicon nitride formed on said layer of silicon dioxide.

9. The method of claim 1, wherein said first, second and third semiconductor materials are all different semiconductor materials.

10. A method of forming a FinFET device, comprising:

providing a substrate comprised of a first semiconductor material;

performing a first epitaxial deposition process to form a layer of a second semiconductor material above said substrate, said second semiconductor material being different than said first semiconductor material;

forming a patterned hard mask layer above said layer of said second semiconductor material;

performing a first etching process through said patterned hard mask layer to define a plurality of spaced-apart trenches that define first and second portions of a fin for said FinFET device, said first portion being comprised of said first semiconductor material, said second portion being comprised of said second semiconductor material;

forming a layer of insulating material in said trenches, said layer of insulating material overfilling said trenches and said patterned hard mask layer;

performing a planarization process on said layer of insulating material that exposes said patterned hard mask layer positioned above said second portion of said fin;

performing at least one second etching process to remove said patterned hard mask layer positioned above said second portion of said fin to thereby expose an upper surface of said second portion of said fin;

performing at least one third etching process to reduce a thickness of said second portion of said fin and thereby define a cavity within said layer of insulating material above said second portion of said fin;

performing a second epitaxial deposition process to form a third portion of said fin on said second portion of said fin within said cavity, said third portion of said fin being comprised of a third semiconductor material that is different than both of said first and second semiconductor materials; and

performing a fourth etching process on said layer of insulating material such that a post-etch upper surface of said layer of insulating material after performing said fourth etching process is performed is below an upper surface of said third portion of said fin.

11. The method of claim 10, wherein said first semiconductor material is comprised of silicon, said second semiconductor material is comprised of one of silicon, silicon/germanium, germanium, a III-V material, a II-VI material, or a combination thereof, and said third semiconductor material is comprised of one of silicon, silicon/germanium, germanium, a III-V material, a II-VI material, or a combination thereof.

12. The method of claim 10, wherein said first semiconductor material is comprised of silicon, and said second semiconductor material is comprised of silicon/germanium with a germanium concentration of 1-99% and said third semiconductor material is comprised of one of silicon, silicon/germanium, germanium, a III-V material, a II-VI material, or a combination thereof.

13. The method of claim 10, wherein said portion of said third portion of said fin that is positioned above said post-etch upper surface of said layer of insulating material defines a final fin height of said FinFET device.

14. The method of claim 10, wherein said post-etch, upper surface of said layer of insulating material is positioned above an upper surface of said second portion of said fin.

15. The method of claim 10, wherein said post-etch, upper surface of said layer of insulating material is positioned below an upper surface of said second portion of said fin.

16. The method of claim 10, wherein performing said planarization process comprises performing a chemical mechanical polishing process.