High-mobility multiple-gate transistor with improved on-to-off current ratio

• US 8,674,341 B2
• Filed: 12/16/2009
• Issued: 03/18/2014
• Est. Priority Date: 04/01/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ko, Chih-Hsin, Wann, Clement Hsingjen
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US12/639,653
• Publication Number:
  US 20100252816A1
• Time in Patent Office: 1,553 Days
• Field of Search: 257/24, 257/29, 257/192, 438/285, 438/287
• US Class Current: 257/24
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/122 Single quantum well structures single heterojunctions, couples of materials H01L29/165, H01L29/205, H01L29/225, H01L29/267
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H01L 29/8124 with multiple gate

Abstract

A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.

Claims

1. A multi-gate transistor comprising:

a substrate;

a semiconductor fin over the substrate and comprising;

a central fin formed of a first semiconductor material; and

a semiconductor layer comprising a first portion and a second portion on opposite sidewalls of the central fin, wherein the semiconductor layer comprises a second semiconductor material different from the first semiconductor material;

a gate electrode wrapping around sidewalls of the semiconductor fin; and

a source region and a drain region on opposite ends of the semiconductor fin, wherein each of the central fin and the semiconductor layer extends from the source region to the drain region.

2. The multi-gate transistor of claim 1, wherein the central fin and the semiconductor layer form a quantum well.

3. The multi-gate transistor of claim 1, wherein the first semiconductor material has a bandgap lower than a bandgap of the second semiconductor material.

4. The multi-gate transistor of claim 1, wherein the first semiconductor material has a conduction band lower than a conduction band of the second semiconductor material.

5. The multi-gate transistor of claim 1, wherein the source region and the drain region are n-type regions.

6. The multi-gate transistor of claim 1 further comprising a gate dielectric comprising a first portion on an outer sidewall of the first portion of the semiconductor layer, and a second portion on an outer sidewall of the second portion of the semiconductor layer.

7. The multi-gate transistor of claim 1, wherein the gate electrode contacts the first portion and the second portion of the semiconductor layer.

8. The multi-gate transistor of claim 1, wherein the semiconductor layer further comprises a third portion on a top surface of the central fin and connecting the first portion of the semiconductor layer to the second portion of the semiconductor layer.

9. The multi-gate transistor of claim 1 further comprising a hard mask on a top surface of the central fin and disconnecting the first portion of the semiconductor layer from the second portion of the semiconductor layer.

10. The multi-gate transistor of claim 9, wherein the hard mask extends directly over the first portion and the second portion of the semiconductor layer.

11. The multi-gate transistor of claim 1 further comprising an additional semiconductor layer comprising:

a first portion between the first portion of the semiconductor layer and the central fin; and

a second portion between the second portion of the semiconductor layer and the central fin, wherein the additional semiconductor layer has a bandgap greater than a bandgap of the central fin, and lower than a bandgap of the semiconductor layer.

12. A multi-gate transistor comprising:

a substrate;

a semiconductor fin over the substrate and comprising;

a central fin formed of a first semiconductor material; and

a semiconductor layer comprising a first portion and a second portion on opposite sidewalls of, and adjoining, the central fin, wherein the semiconductor layer comprises a second semiconductor material different from the first semiconductor material, and wherein the central fin and the semiconductor layer form a quantum well;

a gate dielectric comprising a first portion on an outer sidewall of the first portion of the semiconductor layer, and a second portion on an outer sidewall of the second portion of the semiconductor layer;

a gate electrode over the gate dielectric; and

a source region and a drain region on opposite ends of, and adjoining, the central fin and the semiconductor layer, wherein the source region and the drain region are n-type regions.

13. The multi-gate transistor of claim 12, wherein the central fin extends down into the substrate, and wherein the substrate comprises an insulation region, with the insulation region having an end contacting a sidewall of the central fin, and a top surface contacting a bottom end of the semiconductor layer.

14. The multi-gate transistor of claim 12, wherein the first semiconductor material has a bandgap lower than a bandgap of the second semiconductor material.

15. The multi-gate transistor of claim 14, wherein the first bandgap is lower than the second bandgap by greater than about 0.1 eV.

16. The multi-gate transistor of claim 12, wherein the first semiconductor material has a first conduction band lower than a second conduction band of the second semiconductor material.

17. The multi-gate transistor of claim 12, wherein the central fin has a thickness less than about 10 nm.

18. The multi-gate transistor of claim 12, wherein the semiconductor layer further comprises a third portion on a top surface of the central fin and connecting the first portion of the semiconductor layer to the second portion of the semiconductor layer.

19. The multi-gate transistor of claim 12 further comprising a hard mask on a top surface of the central fin and disconnecting the first portion of the semiconductor layer from the second portion of the semiconductor layer.

20. The multi-gate transistor of claim 12, wherein at least one of the central fin and the semiconductor material comprises a compound semiconductor material comprising a group III element and a group V element.