Lateral devices containing permanent charge

• US 8,674,403 B2
• Filed: 12/04/2012
• Issued: 03/18/2014
• Est. Priority Date: 04/30/2009
• Status: Active Grant

• Current Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: MaxPower Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Darwish, Mohamed N., Paul, Amit
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US13/693,637
• Publication Number:
  US 20140021536A1
• Time in Patent Office: 469 Days
• Field of Search: 257/122, 257/141, 257/331, 257/335, 257/336, 257/339, 257/343, 257/408, 257/409, 257/493
• US Class Current: 257/141
• CPC Class Codes: H01L 21/263 with high-energy radiation H01L21/261 takes precedence
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0873 Drain regions
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region.

Claims

1. A lateral semiconductor device comprising:

a drift region between a body region and a drain region, said drift region having a first conductivity type;

a surface region on an upper surface of the drift region, said surface region having a second conductivity type;

an insulation region over the surface region; and

permanent charges embedded in the insulation region, wherein said permanent charges at least partly deplete the surface region.

2. The lateral semiconductor device of claim 1, wherein said surface region adjoins said body region.

3. The lateral semiconductor device of claim 1, wherein said surface region adjoins said drain region.

4. The lateral semiconductor device of claim 1, wherein said drift region is formed as a well.

5. The lateral semiconductor device of claim 1, further comprising a buried region within said drift region.

6. The lateral semiconductor device of claim 1, further comprising a trench gate.

7. The lateral semiconductor device of claim 6, wherein said trench gate is between said source region and said drain region.

8. The lateral semiconductor device of claim 6, further comprising a buried region within said drift region.

9. The lateral semiconductor device of claim 6, wherein said trench gate extends laterally into said insulation region.

10. The lateral semiconductor device of claim 6, further comprising a gate insulation region wherein a thickness of said gate insulation region adjoining said body region is less than a thickness of said gate insulation region adjoining said drift region.

11. The lateral semiconductor device of claim 8, further comprising a second buried region.