Semiconductor device with lower metal layer thickness in PMOS region

• US 8,674,452 B2
• Filed: 06/24/2011
• Issued: 03/18/2014
• Est. Priority Date: 06/24/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Chien, Chin-Cheng, Lee, Tzung-Ying, Lu, Tsuo-Wen, Chan, Shu-Yen, Chen, Jei-Ming, Lin, Yu-Min, Hsu, Chun-Wei
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): BACHNER, ROBERT G
• Application Number:
  US13/167,738
• Publication Number:
  US 20120326238A1
• Time in Patent Office: 998 Days
• Field of Search: 257/369, 257/368, 257/288, 257/213, 257/E12.632, 257/E21.19, 257/E21.062, 438/229, 438/585
• US Class Current: 257/369
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A semiconductor device includes: a substrate having a first region and a second region; a first gate structure disposed on the first region, wherein the first gate structure comprises a first high-k dielectric layer, a first work function metal layer, and a first metal layer disposed between the first high-k dielectric layer and the first work function metal layer; and a second gate structure disposed on the second region, wherein the second gate structure comprises a second high-k dielectric layer, a second work function metal layer, and a second metal layer disposed between the second high-k dielectric layer and the second work function metal layer, wherein the thickness of the second metal layer is lower than the thickness of the first metal layer.

Claims

1. A semiconductor device, comprising:

a substrate having a first region and a second region;

a first gate structure disposed on the first region, wherein the first gate structure comprises a first high-k dielectric layer, a first work function metal layer, and a first metal layer and a third metal layer disposed between the first high-k dielectric layer and the first work function metal layer, wherein the third metal layer is U-shaped;

a second gate structure disposed on the second region, wherein the second gate structure comprises a second high-k dielectric layer, a second work function metal layer, and a second metal layer disposed between the second high-k dielectric layer and the second work function metal layer, wherein the first metal layer, the second metal layer, and the third metal layer are made of the same material;

a first source/drain disposed in the substrate adjacent to two sides of the first gate structure; and

a second source/drain disposed in the substrate adjacent to two sides of the second gate structure.

2. The semiconductor device of claim 1, wherein the first region comprises a NMOS region and the second region comprises a PMOS region.

3. The semiconductor device of claim 1, further comprising a barrier layer disposed between the first high-k dielectric layer and the first metal layer and between the second high-k dielectric layer and the second metal layer.

4. The semiconductor device of claim 3, wherein the barrier layer comprises TiN.

5. The semiconductor device of claim 1, wherein the first metal layer and the second metal layer comprise TaN.