Semiconductor device and structure

• US 8,674,470 B1
• Filed: 12/22/2012
• Issued: 03/18/2014
• Est. Priority Date: 12/22/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Le, Thao P.
• Application Number:
  US13/726,091
• Time in Patent Office: 451 Days
• Field of Search: 257/499
• US Class Current: 257/499
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01104 Refractory metals
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive layer underneath the second layer, the at least one conductive layer is constructed to provide a back-bias to a portion of the plurality of second single crystal transistors.

Claims

1. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer; and

at least one conductive layer underneath said second layer, said at least one conductive layer is constructed to provide a back-bias to a portion of said plurality of second single crystal transistors.

2. An Integrated Circuit device according to claim 1, wherein said at least one conductive layer comprises a plurality of strips controlled by at least one of said plurality of second single crystal transistors to provide said back-bias.

3. An Integrated Circuit device according to claim 1, wherein said at least one conductive layer comprises a thermal conduction path to said base wafer.

4. An Integrated Circuit device according to claim 1, wherein said at least one conductive layer is constructed to provide shielding for said at least one metal layer from heat resulting from optical annealing of said second layer.

5. An Integrated Circuit device according to claim 1, wherein said at least one conductive layer comprises a refractory metal.

6. An Integrated Circuit device according to claim 1, wherein said at least one conductive layer comprises an electrically conductive path controlled by at least one of said plurality of second single crystal transistors to provide power to at least one of said plurality of second single crystal transistors.

7. An Integrated Circuit device according to claim 1, comprising a plurality of conductive pads overlying at least one of said plurality of second single crystal transistors.

8. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer; and

at least one conductive layer underneath said second layer, said at least one conductive layer is constructed to provide power to at least one of said plurality of second transistors,

wherein said provide power is controlled by at least one of said plurality of second single crystal transistors.

9. An Integrated Circuit device according to claim 8, wherein said at least one conductive layer comprises a plurality of strips to provide a back-bias to a portion of said plurality of second single crystal transistors.

10. An Integrated Circuit device according to claim 8, wherein said at least one conductive layer comprises a thermal conduction path to said base wafer.

11. An Integrated Circuit device according to claim 8, wherein said at least one conductive layer is constructed to provide shielding for said at least one metal layer from heat resulting from optical annealing of said second layer.

12. An Integrated Circuit device according to claim 8, wherein said at least one conductive layer comprises a refractory metal.

13. An Integrated Circuit device according to claim 8, comprising a plurality of conductive pads overlying at least one of said plurality of second single crystal transistors.

14. An Integrated Circuit device according to claim 8, comprising an I/O circuit design adapted to interface with external devices,

wherein said I/O circuit comprises at least one of said plurality of second single crystal transistors.

15. An Integrated Circuit device, comprising:

a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;

at least one metal layer providing interconnection between said plurality of first transistors;

a second layer of less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer;

a plurality of conductive pads overlying at least one of said plurality of second single crystal transistors; and

at least one I/O circuit, said at least one I/O circuit adapted to interface with external devices through at least one of said plurality of conductive pads,

wherein said at least one I/O circuit comprises at least one of said plurality of second single crystal transistors.

16. An Integrated Circuit device according to claim 15, comprising at least one conductive layer underneath said second layer, said at least one conductive layer is constructed to provide a back-bias to a portion of said plurality of second single crystal transistors.

17. An Integrated Circuit device according to claim 15, comprising at least one conductive layer underneath said second layer, wherein said at least one conductive layer comprises a thermal conduction path to said base wafer.

18. An Integrated Circuit device according to claim 15, comprising at least one conductive layer underneath said second layer, wherein said at least one conductive layer is constructed to provide shielding for said at least one metal layer from heat resulting from optical annealing of said second layer.

19. An Integrated Circuit device according to claim 15, comprising at least one conductive layer underneath said second layer, wherein said at least one conductive layer comprises a refractory metal.

20. An Integrated Circuit device according to claim 15, comprising at least one conductive layer underneath said second layer, wherein said at least one conductive layer comprises an electrically conductive path controlled by at least one of said plurality of second single crystal transistors to provide power to at least one of said plurality of second single crystal transistors.