Low harmonic RF switch in SOI

• US 8,674,472 B2
• Filed: 08/10/2010
• Issued: 03/18/2014
• Est. Priority Date: 08/10/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Botula, Alan B., Dang, Dinh, Dunn, James S., Joseph, Alvin J., Lindgren, Peter J.
• Primary Examiner(s): Fulk, Steven J
• Application Number:
  US12/853,532
• Publication Number:
  US 20120038024A1
• Time in Patent Office: 1,316 Days
• Field of Search: 257/522, 257/E21.564, 438/296, 438/422
• US Class Current: 257/522
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 27/0738 in combination with resistors only
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps

Abstract

A low harmonic radio-frequency (RF) switch in a silicon-on-insulator (SOI) substrate and methods of manufacture. A method includes forming at least one trench through an insulator layer. The at least one trench is adjacent a device formed in an active region on the insulator layer. The method also includes forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device.

Claims

1. A method of fabricating a semiconductor structure, comprising:

forming at least one trench through an insulator layer, wherein the at least one trench is adjacent a device formed in an active region on the insulator layer;

forming a mask on and contacting the device;

forming at least one cavity in a substrate under the insulator layer and extending laterally from the at least one trench to underneath the device, wherein the at least one cavity interrupts an interface between the substrate and the insulator layer directly beneath the device; and

filling the at least one trench with a dielectric material without filling the at least one cavity with the dielectric material,

wherein the forming the mask is performed before the forming the at least one cavity, and the mask protects the device during the forming the at least one cavity.

2. The method of claim 1, wherein the forming the at least one cavity comprises isotropically etching the substrate through the at least one trench.

3. The method of claim 2, wherein the forming at least one trench comprises anisotropically etching the insulator layer.

4. The method of claim 2, wherein the isotropic etching comprises etching a material of the substrate selective to a material of the insulator layer.

5. The method of claim 1, further comprising:

removing the mask before the filling the at least one trench.

6. The method of claim 1, wherein the filling the at least one trench with the dielectric material results in at least one of:

formation of voids in the dielectric material in the at least one trench; and

extension of the dielectric material into the at least one cavity.

7. The method of claim 1, wherein the at least one trench is formed through a shallow trench isolation region.

8. The method of claim 1, wherein the substrate, the insulator layer, and the active region are comprised in a semiconductor-on-insulator (SOI) wafer.

9. A method of fabricating a semiconductor structure, comprising:

forming a semiconductor-on-insulator (SOI) wafer including a silicon substrate, an insulator layer on the substrate, and an active semiconductor layer on the insulator layer;

forming an active field effect transistor (FET) device in the active semiconductor layer;

forming at least one trench in a shallow trench isolation region and the insulator layer adjacent the active FET device;

forming a mask on the active FET device and the shallow trench isolation region before the forming the at least one trench; and

disrupting an interface between the substrate and the insulator layer at a location directly underneath the active FET device.

10. The method of claim 9, wherein the disrupting the interface between the substrate and the insulator layer comprises forming at least one cavity in the substrate beneath the insulator layer and at least partially vertically aligned with the active FET device.

11. The method of claim 10, wherein the forming the at least one cavity in the substrate comprises

performing an isotropic etch of the substrate through the at least one trench.

12. The method of claim 9, further comprising at least partially filling the at least one trench with a dielectric material after the disrupting the interface.

13. The method of claim 9, further comprising:

removing the mask after the disrupting the interface.

14. A semiconductor structure, comprising:

a substrate;

an insulator layer on the substrate;

an active device formed in an active semiconductor layer on the insulator layer;

at least one trench extending through a shallow trench isolation region and the insulator layer; and

at least one cavity in the substrate, wherein the at least one cavity is below the insulator layer and extends laterally from the at least one trench to a location that is vertically aligned with the active device, and the at least one cavity interrupts an interface between the substrate and the insulator layer beneath the device,

wherein the at least one trench is filled with dielectric material, and further comprising voids in the dielectric material in the at least one trench.

15. The structure of claim 14, wherein at least one cavity reduces substrate coupling between the active device and the substrate.

16. The structure of claim 14, wherein the substrate, the insulator layer, and the active semiconductor layer are comprised in a semiconductor-on-insulator (SOI) wafer.

17. The structure of claim 14, wherein the active device comprises an RF switch.

18. The structure of claim 14, wherein the shallow trench isolation region defines an island on which the active device is formed.

19. The structure of claim 14, further comprising

extensions of the dielectric material into the at least one cavity.