Semiconductor device including leadframe with downsets

• US 8,674,485 B1
• Filed: 12/08/2010
• Issued: 03/18/2014
• Est. Priority Date: 12/08/2010
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Gi Jeong, Kim, Jae Yoon, Lee, Kyu Won
• Primary Examiner(s): Luu, Chuong A
• Assistant Examiner(s): Doan, Nga
• Application Number:
  US12/963,431
• Time in Patent Office: 1,196 Days
• Field of Search: 257/666, 257/676, 257/670, 257/690, 257/E23.01, 438/123
• US Class Current: 257/676
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/49541 Geometry of the lead-frame
• CPC Class Codes: H01L 23/49551 characterised by bent parts
• CPC Class Codes: H01L 23/49558 Insulating layers on lead frames, e.g. bridging members
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 Encapsulation

Abstract

In one embodiment, a semiconductor package includes a generally planar die paddle or die pad that defines multiple peripheral edge segments, and includes one or more tie bars protruding therefrom. In addition, the semiconductor package includes a plurality of leads, portions of which protrude from respective side surfaces of a package body of the semiconductor package. Connected to the top surface of the die pad is at least one semiconductor die which is electrically connected to at least some of the leads. At least portions of the die pad, the leads, and the semiconductor die are encapsulated by the package body. The one or more tie bars and the plurality of leads include downsets that are sized and oriented relative to each other to facilitate enhanced manufacturing.

Claims

1. A semiconductor package comprising:

a die pad defining multiple peripheral edge segments;

a plurality of inner leads that each include a downset formed therein, the inner leads being segregated into at least two sets that extend along respective ones of at least two peripheral edge segments of the die pad, wherein each of the inner leads defines first and second inner lead regions that are separated by the downset therein, the first inner lead region being disposed between the downset and the die pad, and wherein the first inner lead region of each of the inner leads is longer than the second inner lead region thereof, and wherein the second inner lead regions of the inner leads of each set thereof are of gradually decreasing length as the inner leads are oriented closer toward the center of an adjacent, corresponding peripheral edge segment of the die pad;

at least one tie bar integrally connected to and extending from the die pad, the tie bar including a downset formed therein that is positioned to segregate the tie bar into at least two regions of differing length;

at least one semiconductor die attached to the die pad and electrically connected to at least one of the inner leads; and

a package body defining a peripheral side surface, the package body at least partially encapsulating the die pad, the inner leads, the tie bars and the semiconductor die such that the downsets of the inner leads and the tie bars are covered by the package body.

2. The semiconductor package of claim 1 further comprising a plurality of outer leads integrally connected to respective ones of the inner leads, at least portions of the outer leads protruding from the side surface of the package body.

3. The semiconductor package of claim 1, wherein the semiconductor die is electrically connected to the inner leads by conductive wires that are covered by the package body.

4. The semiconductor package of claim 1, wherein:

the tie bar defines first and second tie bar regions that are separated by the downset therein, the first tie bar region being disposed between the downset and the die pad;

the die pad, the first inner lead regions and the first tie bar region extend in generally co-planar relation to each other;

the second inner lead regions and the second tie bar region extend in generally co-planar relation to each other; and

conductive wires extending from the semiconductor die to respective ones of the first inner lead regions to electrically connect the semiconductor die thereto.

5. The semiconductor package of claim 1, wherein:

the die pad has a generally quadrangular configuration defining four corner regions;

at least four tie bars are integrally connected to and extend diagonally from respective ones of four corner regions of the die pad; and

the inner and outer leads are segregated into at least four sets that each extend along a respective one of the peripheral edge segments of the die pad between an adjacent pair of the tie bars.

6. The semiconductor package of claim 5, wherein:

the second inner lead regions of an outermost pair of the inner leads of each set thereof are each of a first length;

the second inner lead regions of an adjacent central pair of the inner leads of each set that is aligned with the approximate center of a corresponding peripheral edge segment of the die pad are each of a second length that is less than the first length; and

the second inner lead regions of the inner leads of each set that extend between the outermost and central pairs each gradually decrease from the first length to the second length.

7. The semiconductor package of claim 5, wherein:

the second inner lead regions of two outermost groups of the inner leads of each set are of gradually decreasing length; and

the second inner lead regions of the inner leads of each set that are disposed between the outermost groups are of substantially equal length.

8. The semiconductor package of claim 7, wherein the downsets of the inner leads included in each of the two outermost groups of each set are substantially linearly aligned with the downset of the tie bar disposed closest thereto.

9. The semiconductor package of claim 5, wherein:

the second inner lead regions of an outermost pair of the inner leads of each set thereof are each of a first length;

the second inner lead region of a central inner lead of each set that is aligned with the approximate center of a corresponding peripheral edge segment of the die pad is of a second length that is less than the first length; and

the second inner lead regions of the inner leads of each set that extend between the outermost pair and the central inner lead each gradually decrease from the first length to the second length.

10. The semiconductor package of claim 9, wherein the downset of the central inner lead of each set has an angled configuration.

11. The semiconductor package of claim 9, wherein the downset of the central inner lead of each set, and the downsets of two of the inner leads disposed adjacent thereto and extending along respective ones of opposed sides thereof, are each substantially parallel to the adjacent, corresponding peripheral edge segment of the die pad.

12. The semiconductor package of claim 4, wherein the first tie bar region of the tie bar is longer than the second tie bar region thereof.

13. The semiconductor package of claim 1 further comprising a second semiconductor die stacked upon the semiconductor die and electrically connected to at least one of the inner leads.

14. The semiconductor package of claim 13 further comprising a spacer interposed between the semiconductor die and the second semiconductor die.

15. A semiconductor package comprising:

a die pad defining multiple peripheral edge segments;

a plurality of inner leads that each include a downset formed therein, each of the inner leads defines first and second inner lead regions that are separated by the downset therein, the first inner lead region of each of the inner leads being disposed between the downset and the die pad and being longer than the second inner lead region thereof;

a plurality of tie bars integrally connected to and extending from the die pad, each of the tie bars defining first and second tie bar regions that are separated by a downset therein, the first tie bar region of each of the tie bars being disposed between the downset and the die pad and being longer than the second tie bar region thereof, the first inner lead regions being segregated into at least two sets that each extend along a respective one of at least two peripheral edge segments of the die pad and between an adjacent pair of the tie bars, wherein the second inner lead regions of the inner leads of each set thereof are of gradually decreasing length as the inner leads advance toward the center of an adjacent, corresponding peripheral edge segment of the die pad;

at least one semiconductor die attached to the die pad and electrically connected to the first inner lead region of at least one of the inner leads; and

a package body defining a peripheral side surface, the package body at least partially encapsulating the die pad, the inner leads, the tie bars and the semiconductor die such that the downsets of the inner leads and the tie bars are covered by the package body.

16. The semiconductor package of claim 15, wherein:

the second inner lead regions of an outermost pair of the inner leads of each set thereof are each of a first length;

the second inner lead regions of an adjacent central pair of the inner leads of each set that is aligned with the approximate center of a corresponding peripheral edge segment of the die pad are each of a second length that is less than the first length; and

the second inner lead regions of the inner leads of each set that extend between the outermost and central pairs each gradually decrease from the first length to the second length.

17. The semiconductor package of claim 15, wherein:

the second inner lead regions of two outermost groups of the inner leads of each set are of gradually decreasing length; and

the second inner lead regions of the inner leads of each set that are disposed between the outermost groups are of substantially equal length.

18. A semiconductor package comprising:

a die pad;

a plurality of inner leads that each include a downset formed therein, each of the inner leads defines first and second inner lead regions that are separated by the downset therein, the first inner lead region of each of the inner leads being disposed between the downset and the die pad and being longer than the second inner lead region thereof;

a plurality of tie bars integrally connected to and extending from the die pad, each of the tie bars defining first and second tie bar regions that are separated by a downset therein, the first tie bar region of each of the tie bars being disposed between the downset and the die pad and being longer than the second tie bar region thereof, wherein the inner leads are segregated into multiple sets, and the second inner lead regions of the inner leads of each set thereof are of gradually decreasing length as the inner leads advance toward the center of an adjacent, corresponding peripheral edge segment of the die pad;

at least one semiconductor die attached to the die pad and electrically connected to the first inner lead region of at least one of the inner leads; and

a package body defining a peripheral side surface, the package body at least partially encapsulating the die pad, the inner leads, the tie bars and the semiconductor die such that the downsets of the inner leads and the tie bars are covered by the package body, wherein the downsets within the tie bar and the inner leads being sized and oriented relative to each other to minimize the separation between the inner leads and the die pad.

19. The semiconductor package of claim 18, wherein:

the second inner lead regions of an outermost pair of the inner leads of each set thereof are each of a first length;

the second inner lead regions of an adjacent central pair of the inner leads of each set that is aligned with the approximate center of a corresponding peripheral edge segment of the die pad are each of a second length that is less than the first length; and

the second inner lead regions of the inner leads of each set that extend between the outermost and central pairs each gradually decrease from the first length to the second length.

20. The semiconductor package of claim 18, wherein:

the second inner lead regions of two outermost groups of the inner leads of each set are of gradually decreasing length; and

the second inner regions of the inner leads of each set that are disposed between the outermost groups are of substantially equal length.