Three-dimensional integrated circuit structure having improved power and thermal management

• US 8,674,510 B2
• Filed: 07/29/2010
• Issued: 03/18/2014
• Est. Priority Date: 07/29/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Law, Oscar M. K., Wu, Kuo H.
• Primary Examiner(s): ULLAH, ELIAS
• Application Number:
  US12/846,418
• Publication Number:
  US 20120025388A1
• Time in Patent Office: 1,328 Days
• Field of Search: 257/773, 257/777, 257/686, 257/713, 257/173, 257/E23.08, 257/E23.011, 257/118
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10271 : Silicon-germanium [SiGe]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/19041 : being a capacitor

Abstract

A three dimensional (3D) integrated circuit (IC) structure having improved power and thermal management is described. The 3D IC structure includes at least first and second dies. Each of the first and second dies has at least one power through silicon via (TSV) and one signal TSV. The at least one power and signal TSVs of the first die are connected to the at least one power and signal TSVs of the second die, respectively. The 3D IC structure also includes one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die. The peripheral TSV structures supply at least power and/or signals.

Claims

1. A three dimensional (3D) integrated circuit (IC) structure, comprising:

at least first and second dies, each of the first and second dies having at least one power through silicon via (TSV) and one signal TSV, the at least one power TSV and one signal TSV of the first die connected to the at least one power TSV and one signal TSV of the second die, respectively; and

one or more peripheral TSV structures disposed adjacent to one or more sides of the first and/or the second die and configured to supply power or signals to the first and/or second dies, wherein the one or more peripheral TSV structures are separate from the at least first and second dies.

2. The 3D IC structure of claim 1, further comprising an interposer disposed between the first and the second dies.

3. The 3D IC structure of claim 1, wherein the one or more peripheral TSV structures are disposed around the first die and/or the second die.

4. The 3D IC structure of claim 1, wherein the one or more peripheral TSV structures supply at least power and signals.

5. The 3D IC structure of claim 1, further comprising a third die, the third die having at least a power TSV and a signal TSV, the at least one power TSV and one signal TSV of the third die connected to the at least one power TSVs and one signal TSVs of the first and/or second dies, respectively.

6. The 3D IC structure of claim 5, further comprising one or more peripheral TSV structures disposed adjacent to a side of the third die.

7. The 3D IC structure of claim 6, wherein a number of peripheral TSV structures adjacent to the third die is different from a number of peripheral TSV structures adjacent to the second die and a number of peripheral TSV structures adjacent to the first die.

8. The 3D IC structure of claim 6, wherein a number of peripheral TSV structures adjacent to the third die is the same as a number of peripheral TSV structures adjacent to the second die and a number of peripheral TSV structures adjacent to the first die.

9. The 3D IC structure of claim 5, wherein the one or more peripheral TSV structures are disposed around the third die.

10. The 3D IC structure of claim 5, wherein the one or more peripheral TSV structures disposed adjacent to a side of the third die supplies power.

11. The 3D IC structure of claim 5, wherein the one or more peripheral TSV structures disposed adjacent to a side of the third die supplies signals.

12. The 3D IC structure of claim 5, wherein the one or more peripheral TSV structures disposed adjacent to a side of the third die supplies at least power and signal.

13. The 3D IC structure of claim 1, wherein a number of peripheral TSV structures adjacent to the first die is different from a number of peripheral TSV structures adjacent to the second die.

14. The 3D IC structure of claim 1, wherein a number of peripheral TSV structures adjacent to the first die is the same as a number of peripheral TSV structures adjacent to the second die.

15. A 3D IC structure, comprising:

a first die having at least a power TSV and a signal TSV, the first die being surrounded by a plurality of peripheral TSV structures, wherein each peripheral TSV structure of the plurality of peripheral TSV structures is an individual block;

a second die having at least a power TSV and a signal TSV, the second die being surrounded by a plurality of peripheral TSV structures; and

a third die having at least a power TSV and a signal TSV, the third die being surrounded by a plurality of peripheral TSV structures,

wherein the plurality of peripheral TSV structures are configured to supply power or signals.

16. The 3D IC structure of claim 15, further comprising an interposer disposed between the first and second dies.

17. The 3D IC structure of claim 15, wherein the plurality of peripheral TSV structures supply at least power and signals.

18. A 3D IC structure, comprising:

a first die having at least a power TSV and a signal TSV;

one or more peripheral TSV structures disposed separate from and adjacent to one or more sides of the first die;

a second die;

a third die having at least a power TSV and a signal TSV; and

an interposer disposed between the second die and the third die,

wherein the one or more peripheral TSV structures are configured to supply power or signals.

19. The 3D IC structure of claim 18, wherein the one or more peripheral TSV structures are disposed around the first die.

20. The 3D IC structure of claim 18, wherein the one or more peripheral TSV structures supply at least power and signals.