User registers implemented with routing circuits in a configurable IC

• US 8,674,723 B2
• Filed: 12/05/2011
• Issued: 03/18/2014
• Est. Priority Date: 12/01/2005
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US13/311,531
• Publication Number:
  US 20120139580A1
• Time in Patent Office: 834 Days
• Field of Search: 326 37- 41, 326/47
• US Class Current: 326/40
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.

Claims

1. An integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits for configurably performing logic operations; and

a plurality of configurable interconnect circuits for configurably passing signals to and from said configurable logic circuits, the plurality of configurable interconnect circuits connected serially, wherein an output of each configurable interconnect circuit is connected to an input of a subsequent configurable interconnect circuit in the plurality of configurable interconnect circuits, wherein the plurality of configurable interconnect circuits receive and hold a signal for a user clock period, each of the plurality of configurable interconnect circuits holding the signal for one or more sub cycles of the user clock period before passing the signal to a subsequent configurable interconnect circuit in the plurality of configurable interconnect circuits.

2. The IC of claim 1, wherein the plurality of configurable logic circuits form a circuit arrangement, wherein the plurality of configurable interconnect circuits are used for I/O operations that route data between the circuit arrangement and circuits outside of the circuit arrangement.

3. The IC of claim 1, wherein the plurality of configurable interconnect circuits form a user register that receives and holds a signal for a period of time.

4. The IC of claim 3, wherein an input of the user register appears on an output of the user register at one of rising and falling edges of an enable strobe.

5. The IC of claim 1, wherein the plurality of configurable interconnect circuits comprise a master interconnect circuit and a slave interconnect circuit, wherein the master and slave interconnect circuits are enabled in two different sub cycles of the user clock period.

6. The IC of claim 1, wherein the plurality of configurable interconnect circuits comprise four interconnect circuits, each of the four interconnect circuits operating on a different sub cycle of the user clock period.

7. The IC of claim 1, wherein the plurality of configurable interconnect circuits comprise a first and second interconnect circuits, the first and second interconnect circuits operating on four sub cycles of the user clock period, wherein the first interconnect circuit holds a signal for a set of sub cycles of the four sub cycles and passes the signal to the second interconnect circuit to hold for the rest of the four sub cycles.

8. The IC of claim 1, wherein the plurality of configurable interconnect circuits comprise three interconnect circuits, the three interconnect circuits operating on four sub cycles of the user clock period, wherein a first interconnect circuit holds a signal for a set of sub cycles of the four sub cycles and passes the signal to a second interconnect circuit, wherein the second interconnect circuit holds the signal for a set of sub cycles of the four sub cycles and passes the signal to a third interconnect circuit to hold for the rest of the four sub cycles.

9. An integrated circuit (“

IC”

) comprising;

a first set of configurable logic circuits for configurably performing a first set of operations;

a second set of configurable logic circuits for configurably performing a second set of operations; and

a plurality of configurable routing circuits for configurably routing signals from the first set of configurable logic circuits to the second set of configurable logic circuits,

wherein the plurality of configurable routing circuits form a set of user registers that holds a signal from the first set of configurable logic circuits to the second set of configurable logic circuits for a predetermined duration.

10. The IC of claim 9, wherein the predetermined duration comprises a set of clock cycles.

11. The IC of claim 9, wherein a user register of the set of user registers operates as a single edge triggered flip-flop.

12. The IC of claim 9, wherein a user register of the set of user registers operates as a double edge triggered flop-flop.

13. An electronic device comprising:

a memory device that stores configuration data sets; and

an integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits for configurably performing logic operations according to a plurality of the configuration data sets; and

a plurality of configurable interconnect circuits for configurably passing signals to and from said configurable logic circuits, the plurality of configurable interconnect circuits connected serially, wherein an output of each configurable interconnect circuit is connected to an input of a subsequent configurable interconnect circuit in the plurality of configurable interconnect circuits, wherein the plurality of configurable interconnect circuits receive and hold a signal for one user clock period, each of the plurality of configurable interconnect circuits holding the signal for one or more sub cycles before passing the signal to a subsequent configurable interconnect circuit in the plurality of configurable interconnect circuits.

14. The electronic device of claim 13, wherein the plurality of configurable logic circuits form a circuit arrangement, wherein the plurality of configurable interconnect circuits are used for I/O operations that route data between the circuit arrangement and circuits outside of the circuit arrangement.

15. The electronic device of claim 13, wherein the plurality of configurable interconnect circuits form a user register that receives and holds a signal for a period of time.

16. The electronic device of claim 15, wherein an input of the user register appears on an output of the user register at one of rising and falling edges of an enable strobe.

17. The electronic device of claim 13, wherein the plurality of configurable interconnect circuits comprise a master interconnect circuit and a slave interconnect circuit, wherein the master and slave interconnect circuits are enabled in two different sub cycles of the user clock period.

18. The electronic device of claim 13, wherein the plurality of configurable interconnect circuits comprise four interconnect circuits, each of the four interconnect circuits operating on a different sub cycle of the user clock period.

19. The electronic device of claim 13, wherein the plurality of configurable interconnect circuits comprise a first and second interconnect circuits, the first and second interconnect circuits operating on four sub cycles of the user clock period, wherein the first interconnect circuit holds a signal for a set of sub cycles of the four sub cycles and passes the signal to the second interconnect circuit to hold for the rest of the four sub cycles.

20. The electronic device of claim 13, wherein the plurality of configurable interconnect circuits comprise three interconnect circuits, the three interconnect circuits operating on four sub cycles of the user clock period, wherein a first interconnect circuit holds a signal for a set of sub cycles of the four sub cycles and passes the signal to a second interconnect circuit, wherein the second interconnect circuit holds the signal for a set of sub cycles of the four sub cycles and passes the signal to a third interconnect circuit to hold for the rest of the four sub cycles.