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System for embedded video test pattern generation

  • US 8,675,076 B2
  • Filed: 07/19/2010
  • Issued: 03/18/2014
  • Est. Priority Date: 07/21/2009
  • Status: Active Grant
First Claim
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1. A video processing circuit, comprising:

  • a synchronization generator to generate a clock signal selectively based on one of an input video stream clock signal and an alternate clock signal, the alternate clock signal being selectively chosen from one of a plurality of clock signals; and

    a test pattern generator coupled to receive the clock signal provided by the synchronization generator and to generate a test pattern over a number of cycles, the test pattern generator including at least two accumulators coupled in series, such that one of the at least two accumulators receives only an output from another of the at least two accumulators.

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