System for embedded video test pattern generation
First Claim
1. A video processing circuit, comprising:
- a synchronization generator to generate a clock signal selectively based on one of an input video stream clock signal and an alternate clock signal, the alternate clock signal being selectively chosen from one of a plurality of clock signals; and
a test pattern generator coupled to receive the clock signal provided by the synchronization generator and to generate a test pattern over a number of cycles, the test pattern generator including at least two accumulators coupled in series, such that one of the at least two accumulators receives only an output from another of the at least two accumulators.
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Abstract
In accordance with some embodiments of the invention, a video processing circuit can include a synchronization generator to generate a clock signal from an input video stream; and a test pattern generator coupled to receive the clock signal provided by the synchronization generator and to generate a test pattern over a number of cycles. In accordance with some embodiments of the present invention, a video processing system may include an video input capture circuit; a video input processing circuit including a synchronization generator and a test pattern generator; a video scaling circuit; a video merging circuit to recombine the video signals provided by the video scaling circuit into one video signal; and a video output circuit including a cyclical redundancy check circuit.
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Citations
18 Claims
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1. A video processing circuit, comprising:
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a synchronization generator to generate a clock signal selectively based on one of an input video stream clock signal and an alternate clock signal, the alternate clock signal being selectively chosen from one of a plurality of clock signals; and a test pattern generator coupled to receive the clock signal provided by the synchronization generator and to generate a test pattern over a number of cycles, the test pattern generator including at least two accumulators coupled in series, such that one of the at least two accumulators receives only an output from another of the at least two accumulators. - View Dependent Claims (2, 3, 4, 5, 16, 17, 18)
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6. A video processing system, comprising:
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a video input capture circuit; a video input processing circuit comprising a synchronization generator and a test pattern generator, the test pattern generator including at least two accumulators coupled in series, such that one of the at least two accumulators receives only an output from another of the at least two accumulators; a video scaling circuit; a video merging circuit to recombine the video signals provided by the video scaling circuit into one video signal; and a video output circuit comprising a cyclical redundancy check circuit. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
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15. A method to generate test patterns comprising the steps of:
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generating a pseudo random number to provide variability to the test patterns; providing initial values to at least one register to generate the test patterns; determining a number of cycles to use for generating the test patterns with a test pattern generator; providing values from previous cycles using at least two accumulators coupled in series, such that one of the at least two accumulators receives only an output from another of the at least two accumulators; selecting a test pattern using a mode configuration block; and obtaining a digital signature from an input video frame and the test pattern by using a lookup table.
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Specification